
17
 Regulators 1,2
OPERATION
R
OUT4
I
BC1,2
V
DD
R2
R1
GND
CSW1,2
Level
 Shift
R
OUT1,2
Current
 Limit
Circuit
V
+
–
C
1,2
Each of Regulators 1 and 2 is operating with an external PNP transistor as shown in the above figure.
Regulators 1 and 2 divide Output Voltage V
OUT
 by Feed-back Registers R1 and R2, and the divided voltage at the
node between Registers R1 and R2 is compared with the reference voltage by Error Amplifier, so that the base cur-
rent of the PNP transistor is adjusted, and a constant voltage is output.  The output current from each of
Regulators 1 and 2 is monitored by Current Limitter, and when the output current exceeds a limit current,
Current Limitter limits the base current of the PNP transistor to the specified limit current. 
The level of input signals to CSW 1, 2 is set at the same level as the output voltage level of R
OUT
4
 by built-in
level shift circuit.
Phase compensation is made externally with C
1,2
.
 Regulators 3,4
V
CSW3
R
OUT4
V
DD
R2
R1
GND
A
R
OUT3,4
Current
 Limit
Circuit
Level
 Shift
+
–
Regulators 3 and 4 divide Output Voltage V
OUT
 by feed-back Registers R1 and R2, and the divided voltage at
the node between Registers R1 and R2 is compared with the reference voltage by Error Amplifier, so that a con-
stant voltage is output.  The output current from each of Regulators 3 and 4 is monitored by Current Limitter, and
when the output current exceeds a limit current, Current Limitter limits the output current to the limit current.
Regulator 4 is connected at Point to the GND in the above figure, so that Regulator 4 is always in operation. 
The level of input signals to CSW1, 2 is set at the same level as the output voltage level of R
OUT
4
by built-in lev-
el shift circuits.
RV5VE0
×××