參數(shù)資料
型號: RV5C338A
廠商: RICOH COMPANY LTD
元件分類: XO, clock
英文描述: 3-WIRE SERIAL INTERFACE REAL-TIME CLOCK ICs WITH VOLTAGE MONITORING FUNCTION
中文描述: REAL TIME CLOCK, PDSO10
封裝: 4 X 2.90 MM, 1.20 MM HEIGHT, SSOP-10
文件頁數(shù): 40/52頁
文件大?。?/td> 440K
代理商: RV5C338A
37
R
×
5C338A
Approx. 92
μ
s
CTFG bit
INTR pin
(Increment of second counter)
Rewriting of the second counter
Relation Between the Mode Waveform and the CTFG Bit
Pulse mode
*
) In the pulse mode, the increment of the second counter is delayed by approximately 92 μs from the falling edge of clock pulses. Consequently, time
readings immediately after the falling edge of clock pulses may appear to lag behind the time counts of the real-time clocks by approximately 1 second.
Rewriting the second counter will reset the other time counters of less than 1 second, driving the INTR pin low.
Setting CTFG bit to 0
(Increment of
second counter)
Setting CTFG bit to 0
CTFG bit
INTR pin
(Increment of
second counter)
(Increment of
second counter)
5. 32-kHz Clock Output
32.768-kHz clock pulses are output from the 32KOUT pin when either the CLEN1 bit in the control register 2 or the
CLEN2 bit in the control register 1 is set to 0 when the CLKC pin is set to high. If the conditions described above
are not satisfied, the output is set to high.
CLEN1
CLEN2
CLKC pin output
32KOUT pin output
(CMOS output)
(D3 at Address Fh)
(D4 at Address Eh)
1
1
*
“L”
*
*
0
0 (Default)
*
1
Clock pulses
*
0 (Default)
1
The 32KOUT pin output is synchronized with the CLEN1, CLEN2 bit, and CLKC pin settings as illustrated in the tim-
ing chart below.
MAX. 76.3
μ
s
32KOUT pin output
CLKC pin or
CLEN1 or CLEN2 bit setting
Level mode
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