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參數(shù)資料
| 型號： | RV5C338A |
| 廠商： | RICOH COMPANY LTD |
| 元件分類： | XO, clock |
| 英文描述： | 3-WIRE SERIAL INTERFACE REAL-TIME CLOCK ICs WITH VOLTAGE MONITORING FUNCTION |
| 中文描述： | REAL TIME CLOCK, PDSO10 |
| 封裝： | 4 X 2.90 MM, 1.20 MM HEIGHT, SSOP-10 |
| 文件頁數(shù)： | 35/52頁 |
| 文件大小： | 440K |
| 代理商： | RV5C338A |
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5C338A
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3. Oscillation Halt Sensing and Supply Voltage Monitoring
The oscillation halt sensing circuit is configured to record a halt in the oscillation of 32.768-kHz clock pulses. The
supply voltage monitoring circuit is configured to record a drop in supply voltage below a threshold voltage of 2.1 or
1.6 volts. For these functions, the real-time clock has two flag bits (i.e. the XSTP bit for the former and the VDET bit
for the latter) in which 1 is set once and this setting is maintained until 0 is written.
When the XSTP bit is set to 1 for the oscillation halt sensing circuit, the VDET bit is reset to 0 for the supply voltage
monitoring circuit. The relationship between the XSTP and VDET bits is shown in the table below.
The Oscillation halt sensing circuit operates only when the CE pin is Low. The sensing result is maintained after
the CE pin changes from “L” to “H” (See “6.4 Connection of CE Pin”).
XSTP
VDET
Conditions of supply voltage and oscillation
0
0
No drop in supply voltage below threshold voltage and no halt in oscillation
0
1
Drop in supply voltage below threshold voltage and no halt in oscillation
1
*
Halt on oscillation
Supply voltage
Threshold voltage (2.1 or 1.6 volts)
Setting XSTP and
VDET bits to 0
Setting XSTP and
VDET bits to 0
Internal initialization
period
(1 to 2 seconds)
Setting VDET bit to 0
Oscillation by 32.768-kHz clock pulses
Normal voltage detector
Supply voltage monitoring (VDET)
Oscillation halt sensing (XSTP)
When the XSTP bit is set to 1 in the control register 2, the (0), F
6
to F
0
, WALE, DALE, 12/24, CLEN2, TEST, CT2,
CT1, CT0, VDSL, VDET, SCRATCH, CLEN1, CTFG, WAFG, and DAFG bits are reset to 0 in the oscillation
adjustment register, the control register 1, and the control register 2. When the CE pin is “H” at power on from 0
volts, the XSTP bit is undefined, and the above bits are undefined (See “6.4 Connection of CE Pin”). The XSTP bit is
also set to 1 at power-on from 0 volts. Note that the XSTP bit may be locked to 0 and the internal register broken
upon instantaneous power-down.
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PDF描述 |
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| RV5C338A-E2 | DIODE ZENER SINGLE 200mW 8.2Vz 20mA-Izt 0.02549 0.1uA-Ir 6.5 SOD-323 3K/REEL |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RV5C338A-E2 | 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:3-WIRE SERIAL INTERFACE REAL-TIME CLOCK ICs WITH VOLTAGE MONITORING FUNCTION |
| RV5C339 | 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:3-WIRE SERIAL INTERFACE REAL-TIME CLOCK ICs WITH VOLTAGE MONITORING FUNCTION |
| RV5C339A | 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:3-WIRE SERIAL INTERFACE REAL-TIME CLOCK ICs WITH VOLTAGE MONITORING FUNCTION |
| RV5C339A_03 | 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:3-WIRE SERIAL INTERFACE REAL-TIME CLOCK IC WITH VOLTAGE MONITORING FUNCTION |
| RV5C339A-E2 | 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:3-WIRE SERIAL INTERFACE REAL-TIME CLOCK ICs WITH VOLTAGE MONITORING FUNCTION |
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