參數(shù)資料
型號: RS5C348B-E2
廠商: RICOH COMPANY LTD
元件分類: XO, clock
英文描述: Real-Time Clock
中文描述: 0 TIMER(S), REAL TIME CLOCK, PDSO10
封裝: 6.40 X 3.50 MM, 1.25 MM HEIGHT, 0.5 MM PITCH, SSOP-10
文件頁數(shù): 41/53頁
文件大小: 452K
代理商: RS5C348B-E2
R
×
5C348A/B
38
Setting CTFG bit to 0
(Increment of
second counter)
(Increment of
second counter)
(Increment of
second counter)
CTFG bit
INTR pin
Setting CTFG bit to 0
5. 32-kHz Clock Output
For the R
×
5C348A, 32.768-kHz clock pulses are output from the 32KOUT pin when either the CLEN1 bit in the
control register 2 or the CLEN2 bit in the control register 1 is set to 0. When both the CLEN1 and CLEN2 bits are
set to 0, the 32KOUT pin output is driven high (disabled) For the R
×
5C348B, 32.768-kHz clock pulses are output
from the 32KOUT pin regardless of such internal register settings.
CLEN1 bit setting
(D3 at address Fh)
CLEN2 bit setting
(D4 at address Eh)
32KOUT pin output
(for the R
×
5C348A)
(Nch. open drain output)
32KOUT pin output
(for the R
×
5C348B)
(Nch. open drain output)
1
1
OFF(“H”)
Clock pulses
0 (Default)
*
Clock pulses
*
0 (Default)
For the R
×
5C348A, the 32KOUT pin output is synchronized with the CLEN1 and CLEN2 bit settings as illustrated
in the timing chart below.
MAX. 61.0
μ
s
MAX. 45.8
μ
s
CLEN1 or CLEN2 bit setting
32KOUT pin output
Level Mode
Approx. 92
μ
s
CTFG bit
INTR pin
(Increment of second counter)
Rewriting of the second counter
Relation Between the Mode Waveform and the CTFG Bit
Pulse Mode
*
) In the pulse mode, the increment of the second counter is delayed by approximately 92 μs from the falling edge of clock pulses. Consequently, time
readings immediately after the falling edge of clock pulses may appear to lag behind the time counts of the real-time clocks by approximately 1 second.
Rewriting the second counter will reset the other time counters of less than 1 second, driving the INTR pin low.
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