- 您現在的位置：買賣IC網 > PDF目錄384890 > RS5C348B-E2 (RICOH COMPANY LTD) Real-Time Clock PDF資料下載
參數資料
| 型號： | RS5C348B-E2 |
| 廠商： | RICOH COMPANY LTD |
| 元件分類： | XO, clock |
| 英文描述： | Real-Time Clock |
| 中文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO10 |
| 封裝： | 6.40 X 3.50 MM, 1.25 MM HEIGHT, 0.5 MM PITCH, SSOP-10 |
| 文件頁數： | 19/53頁 |
| 文件大?。?/td> | 452K |
| 代理商： | RS5C348B-E2 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁當前第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁
R
×
5C348A/B
16
WAFG, DAFG
Description
0
Indicating a mismatch between current time and preset alarm time
1
Indicating a match between current time and preset alarm time
2.2-7 WAFG and DAFG
Alarm_W Flag Bit and Alarm_D Flag Bit
(Default setting)
The WAFG and DAFG bits are valid only when the WALE and DALE bits have the setting of 1, which is caused
approximately 61μs after any match between current time and preset alarm time specified by the Alarm_W registers
and the Alarm_D registers. The WAFG and DAFG bits accept only the writing of 0, which disables (“H”) the INTR
pin until it is enabled (“L”) again at the next preset alarm time. Conversely, setting the WAFG and DAFG bits to 1
causes no event. The WAFG and DAFG bits will have the reading of 0 when the alarm interrupt circuit is disabled
with the WALE and DALE bits set to 0. The settings of the WAFG and DAFG bits are synchronized with the output
of the INTR pin as shown in the timing chart below.
Output Relationships Between the WAFG or DAFG Bit and INTR
Writing of 0 to WAFG
(DAFG) bit
Writing of 0 to WAFG
(DAFG) bit
(
Match between current time
and preset alarm time
)
(
Match between current time
and preset alarm time
)
(
Match between current time
and preset alarm time
)
Settings of WAFG (DAFG) bit
Output of INTR pin
Approx.61
μ
s
Approx.61
μ
s
CTFG
Description
0
Periodic interrupt output “H” (OFF)
1
Periodic interrupt output “L” (ON)
2.2-6 CTFG
Periodic Interrupt Flag Bit
(Default setting)
The CTFG bit is set to 1 when the periodic interrupt signals are output from the INTR pin (“L”). The CTFG bit
accepts only the writing of 0 in the level mode, which disables (“H”) the INTR pin until it is enabled (“L”) again in
the next interrupt cycle. Conversely, setting the CTFG bit to 1 causes no event.
相關PDF資料 |
PDF描述 |
|---|---|
| RT1710B6 | LVDS & LVPECL FPGA Terminator RoHS Compliant Parts Available |
| RT1710B7 | LVDS & LVPECL FPGA Terminator RoHS Compliant Parts Available |
| RT1720B7 | LVDS & LVPECL FPGA Terminator RoHS Compliant Parts Available |
| RT1721B6 | LVDS & LVPECL FPGA Terminator RoHS Compliant Parts Available |
| RT1721B7 | LVDS & LVPECL FPGA Terminator RoHS Compliant Parts Available |
相關代理商/技術參數 |
參數描述 |
|---|---|
| RS5C372A | 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:I2C bus SERIAL INTERFACE REAL-TIME CLOCK ICs |
| RS5C372B | 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:I2C-bus Serial Interface Real Time Clock (8pin SSOP) |
| RS5C372B-E1 | 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:I2C-bus Serial Interface Real Time Clock (8pin SSOP) |
| RS5C372B-E2 | 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:I2C-bus Serial Interface Real Time Clock (8pin SSOP) |
| RS5C373A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Real-Time Clock |
發(fā)布緊急采購，3分鐘左右您將得到回復。