參數(shù)資料
型號: RS5C316
廠商: Ricoh Co., Ltd.
英文描述: MINIATURE POWER RELAY
中文描述: 超緊湊報(bào)警串行實(shí)時(shí)時(shí)鐘IC
文件頁數(shù): 11/38頁
文件大?。?/td> 288K
代理商: RS5C316
RS5C316A/B
7
FUNCTIONAL DESCRIPTIONS
1. Addressing
Address
Registers
Data *
1
A3
A2
A1
A0
D3
D2
D1
D0
0
0
0
0
0
1-second counter
(BANK=0)
S
8
S
4
S
2
S
1
Day of the week alarm register 1
(BANK=1)
AW
3
AW
2
AW
1
AW
0
1
0
0
0
1
10-second counter
(BANK=0)
—*
2
S
40
S
20
S
10
Day of the week alarm register 2
(BANK=1)
ALC
AW
6
AW
5
AW
4
2
0
0
1
0
1-minute counter
(BANK=0)
M
8
M
4
M
2
M
1
1-minute alarm register
(BANK=1)
AM
8
AM
4
AM
2
AM
1
3
0
0
1
1
10-minute counter
(BANK=0)
M
40
M
20
M
10
10-minute alarm register
(BANK=1)
AM
40
AM
20
AM
10
4
0
1
0
0
1-hour counter
(BANK=0)
H
8
H
4
H
2
H
1
1-hour alarm register
(BANK=1)
AH
8
AH
4
AH
2
AH
1
5
0
1
0
1
10-hour counter
(BANK=0)
P/A, H
20
H
10
10-hour alarm register
(BANK=1)
ALE
AP/A, AH
20
AH
10
6
0
1
1
0
Day of the week counter
(BANK=0)
W
4
W
2
W
1
7
0
1
1
1
Interrupt cycle register
(BANK=0, 1)
CT
3
CT
2
CT
1
CT
0
8
1
0
0
0
1-day counter
(BANK=0)
D
8
D
4
D
2
D
1
9
1
0
0
1
10-day counter
(BANK=0)
D
20
D
10
A
1
0
1
0
1-month counter
(BANK=0)
MO
8
MO
4
MO
2
MO
1
B
1
0
1
1
10-month counter
(BANK=0)
MO
10
C
1
1
0
0
1-year counter
(BANK=0)
Y
8
Y
4
Y
2
Y
1
D
1
1
0
1
10-year counter
(BANK=0)
Y
80
Y
40
Y
20
Y
10
E
1
1
1
0
Control register 1
(BANK=0, 1)
CTFG
ALFG
WTEN
*
6
/XSTP
*
4
ADJ/BSY *
3
F
1
1
1
1
Control register 2
(BANK=0, 1)
12/24
NOP
BANK *
5
TEST *
6
*
1) All the listed data can be read and written.
*
2) The “—” mark indicates data which can be read only and set to “0” when read.
*
3) The ADJ/BSY bit of the control register is set to ADJ for write operation and BSY for read operation.
*
4) The WTEN/XSTP bit of the control register is set to WTEN for write operation and XSTP for read operation.
*
5) The clock/calendar counter and the alarm register can be selected when the BANK=0 and BANK=1 respectively. To designate the BANK is unnec-
essary for interrupt cycle register and control register 1/2.
*
6) The WTEN bit and TEST bit are set to “1” when CE is “L”.
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