參數(shù)資料
型號(hào): RM009
廠商: SKYWORKS SOLUTIONS INC
元件分類: 放大器
英文描述: Power Amplifier Module for Dual-band GSM900 DCS1800
中文描述: 880 MHz - 915 MHz RF/MICROWAVE NARROW BAND MEDIUM POWER AMPLIFIER
封裝: 9.10 X 11.60 MM, SO-16
文件頁(yè)數(shù): 5/17頁(yè)
文件大小: 304K
代理商: RM009
RM009
Technical Information
Power Amplifier Module for Dual-band GSM900 DCS1800 Applications
101258B
Skyworks Solutions, Inc. Proprietary
13
July 26, 2002
requirement to limit the edge rate of output power transitions of the mobile. Switching transients
are caused by the transition from minimum output power to the desired output power, and vice
versa. The spectrum generated by this transition is due to the ramping waveform amplitude
modulation imposed on the carrier. Sharper transitions tend to produce more spectral "splatter"
than smooth transitions. If the transmit output power is ramped up too slowly, the radio will violate
the time mask specification. In this condition, the radio may not successfully initiate or maintain a
phone call. If the transmit output power is ramped up too quickly, this will cause RF "splatter" at
certain frequency offsets from the carrier as dictated by the 3GPP specification. This splatter,
known as Output RF Spectrum (ORFS) due to Switching Transients, will increase the system noise
level, which may knock out other users on the system. The main difficulty with TDMA power
control is allowing the transmitter to ramp the output power up and down gradually so switching
transients are not compromised while meeting the time mask template at all output power levels in
all operational bands. The transmitter has 28
sec to ramp up power from an off state to the desired
power level.
The GSM transmitter power control loop generally involves feedback around the GaAs PA, which
limits the bandwidth of signals that can be applied to the PA bias input. Since the PA is within the
feedback loop, its own small-signal frequency response must exhibit a bandwidth 5 to 10 times that
of the power control loop. As discussed in the previous section, the PA bias is held at ground for
inputs less than 700mV. As the APC input exceeds the enable threshold, the bias will activate.
After an 8
s delay, the amplifier internal bias will quickly ramp to match the ramp voltage applied
to the VAPC input. Since the bias must be wide band relative to the power control loop, the ramp
will exhibit a fast edge rate. If the APC input increases beyond 1V before the 8
s switching delay
is allowed to occur after the bias is enabled, the PA will have significant RF output as the internal
bias approaches the applied bias. During this ramp, the internal power control is running "open
loop" and the edge rates are defined by the frequency response of the PA bias rather than that of the
power control loop. This open loop condition will result in switching transients that are directly
correlated to the PA bias bandwidth.
Application of an initial APC voltage, which enables the bias at least 8
s before the VAPC voltage
is ramped, will ensure that the internal bias of the PAM will directly follow the applied VAPC. As a
result, the power control loop will define all edge transitions rather than the PA internal bandwidth
defining the transition. Figures 10 and 11 show the relationship of the internal bias relative to the
applied APC in two cases. One case has ramping starting from ground; the other case has ramping
starting with an initial enable pedestal of 700 mV. It is evident that the pedestal level is critical to
ensure a predictable and well behaved power control loop.
To enable the CMOS driver in the PAM prior to ramp-up, a PAC output pedestal level to the
APC input of the PAM (pin 14) should be set to about 700 mV. This pedestal level should
have a duration of at least 8
sec directly prior to the start of ramp up.
Figure 12 shows typical signals and timings measured in a GSM transmitter power control loop.
This particular example is at GSM Power Level 5, Channel 62. The oscilloscope traces are
TxVCO_enable, PAC_enable, DAC Ramp, and VAPC (pin 14).
NOTE:
When the TxVCO is enabled, the pedestal becomes set at the APC input of the PAM, then
the PAC is enabled, and finally the DAC ramp begins.
The device specifications for enable threshold level and switching delay are shown in Table 3.
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