參數(shù)資料
型號(hào)： RK80532PC041512
英文描述： Microprocessor
中文描述： 微處理器
文件頁(yè)數(shù)： 49/86頁(yè)
文件大?。?/td> 882K
代理商： RK80532PC041512
Datasheet
49
Intel
Pentium
III Processor with 512KB L2 Cache at 1.13GHz to 1.40GHz
3.4
Non-AGTL Signal Quality Specifications and Measurement
Guidelines
There are three signal quality parameters defined for non-AGTL signals: overshoot/undershoot,
ringback, and settling limit. All three signal quality parameters are shown in
Figure 21
for the non-
AGTL signal group.
NOTE:
1. V
= 1.80 V for all non-AGTL signals except for BCLK, PICCLK, and PWRGOOD. V
=2.0 V for PICCLK,
and V
HI
=1.8 V for PWRGOOD. BCLK and PICCLK signal quality is detailed in
Section 3.1
.
3.4.1
Overshoot/Undershoot Guidelines
Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high
voltage or below V
SS
. The overshoot guideline limits transitions beyond V
CC
or V
SS
due to the fast
signal edge rates (see
Figure 21
for non-AGTL signals). The processor can be damaged by repeated
overshoot events on 1.25V or 1.8V tolerant buffers if the charge is large enough (i.e., if the
overshoot is great enough). Permanent damage to the processor is the likely result of excessive
overshoot/undershoot. Violating the overshoot/undershoot guideline will also make satisfying the
ringback specification difficult.
The overshoot/undershoot guideline is 0.3V
and assumes the
absence of diodes on the input. These guidelines should be verified in simulations
without the on-
chip ESD protection diodes present
because the diodes will begin clamping the 1.25V and 2.5V
tolerant signals beginning at approximately 0.7V above the appropriate supply and 0.7V below
V
SS
. If signals are not reaching the clamping voltage, this will not be an issue. A system should not
rely on the diodes for overshoot/undershoot protection as this will negatively affect the life of the
components and make meeting the ringback specification very difficult.
Figure 21. Non-AGTL Overshoot/Undershoot, Settling Limit, and Ringback
1
Undershoot
Overshoot
Settling Limit
Settling Limit
Rising-Edge
Ringback
Falling-Edge
Ringback
V
LO
V
SS
Time
V
HI
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