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參數(shù)資料
| 型號： | RK80532PC041512 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 18/86頁 |
| 文件大小： | 882K |
| 代理商： | RK80532PC041512 |
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18
Datasheet
Intel
Pentium
III Processor with 512KB L2 Cache at 1.13GHz to 1.40GHz
2.6
Voltage Identification
There are five voltage identification (VID) pins on the PGA370 socket. These pins can be used to
support automatic selection of V
CCCORE
voltages. The VID pins for the Intel Pentium
III
processor with 512KB L2 Cache are open drain signals versus opens or shorts found on the
previous Intel
Pentium
III
processors in the FC-PGA package. Refer to
Table 11
for level
specifications for the VID signals. This pull-up resistor may be either external logic on the
motherboard or internal to the Voltage Regulator.
The VID signals rely on a 3.3V pull-up resistor to set the signal to a logic high level. The VID pins
are needed to fully support voltage specification variations on current and future processors. The
voltage selection range for the processor is defined in
Table 3
. The VID25mV signal is a new
signal that allows the voltage regulator or voltage regulator module (VRM) to output voltage levels
in 25mV increment necessary for the Intel Pentium
III
processor with 512KB L2 Cache only.
The legacy Pentium
III
processor in the FC-PGA package will not have this VID25mV signal.
The VID25mV pin location is actually a Vss pin on the Pentium
III
processor (CPUID = 068xh).
By connecting the VID25mV signal to the Vss pin, it will disable the 25mV stepping granularity
output and the regulator will resort to 50mV stepping increment. The voltage regulator or VRM
must supply the voltage that is requested or disable itself.
In addition to the new signal “VID25mV”, the Intel Pentium
III
processor with 512KB L2
Cache will introduce a second new signal labeled as “VTT_PWRGD”. The VTT_PWRGD signal
informs the platform that the VID and BSEL signals are stable and should be sampled. During
power-up, the VID signals will be in an indeterminate state for a small period of time. The voltage
regulator or the VRM should not latch the VID signals until the VTT_PWRGD signal is asserted
by the VRM and sampled active. The assertion of the VTT_PWRGD signal indicates the VID
signals are stable and are driven to the final state by the processor. Refer to
Figure 14
for power-up
timing sequence for the VTT_PWRGD and the VID signals.
Figure 5. Differential/Single-Ended Clocking Example
BCLK
BCLK#
Clock
Driver
Processor or
Chipset
Clock
Driver
BCLK
Processor
orChipset
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