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參數(shù)資料
| 型號： | RHF1201KSO2 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | ADC |
| 英文描述： | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO48 |
| 封裝： | LEAD FREE, HERMETIC SEALED, SOP-48 |
| 文件頁數(shù)： | 24/26頁 |
| 文件大?。?/td> | 328K |
| 代理商： | RHF1201KSO2 |
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RHF1201
Timing characteristics
7/26
5
Timing characteristics
Figure 7.
Timing diagram
Table 2.
Timing table
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
FS
Sampling frequency
0.5
50
Msps
Tck
Sampling clock cycle
20
2000
ns
DC
Clock duty cycle(1)
1.
For any clock frequency and any duty cycle the high level clock pulse must be longer than 10 ns.
FS = 45 Msps
45
50
65
%
TC1
Clock pulse width (high)
10
1800
ns
TC2
Clock pulse width (low)
8
1800
ns
Tod
Data output delay
(fall of clock to data valid)
10 pF load
4
5
6
ns
Tpd
Data pipeline delay
5.5
cycles
Tdr
Data ready delay after data
change
0.5
cycles
Ton
Falling edge of OEB to
digital output valid data
13
ns
Toff
Rising edge of OEB to
digital output tri-state
13
ns
TrD
Data rising time
5 pF load, SRC = 0
2.8
ns
5 pF load, SRC = 1
5.7
ns
TfD
Data falling time
5 pF load, SRC = 0
2
ns
5 pF load, SRC = 1
4.3
ns
N-3
N-2
N-1
N+4
N+5
N
N+3
N+1
N+2
N+6
N-3
N-1
N-4
N-5
N-6
N-7
N-8
N-9
CLK
OEB
DR
Tod
Ton
Toff
Tpd + Tod
HZ state
N
DATA
OUT
Tdr
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