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| 型號： | RG82870P2 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 73/157頁 |
| 文件大小： | 1407K |
| 代理商： | RG82870P2 |
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Intel
82845MP/82845MZ Chipset-Mobile (MCH-M)
22
Datasheet
250687-002
R
Signal Name
Type
Description
HD[63:0]#
I/O
AGTL+ 4x
Host Data: These signals are connected to the system data bus. HD[63:0]# are
transferred at 4x rate. Note that the data signals are inverted on the system bus.
HDSTBP[3:0]#
HDSTBN[3:0]#
I/O
AGTL+ 4x
Differential Host Data Strobes: The differential source synchronous strobes used
to transfer HD[63:0]# and DBI[3:0]# at the 4x transfer rate.
Strobe
Data Bits
HDSTBP3#, HDSTBN3#
HD[63:48]#, DBI3#
HDSTBP2#, HDSTBN2#
HD[47:32]#, DBI2#
HDSTBP1#, HDSTBN1#
HD[31:16]#, DBI1#
HDSTBP0#, HDSTBN0#
HD[15:0]#, DBI0#
HIT#
I/O
AGTL+
Hit: Indicates that a caching agent holds an unmodified version of the requested
line. Also, driven in conjunction with HITM# by the target to extend the snoop
window.
HITM#
I/O
AGTL+
Hit Modified: Indicates that a caching agent holds a modified version of the
requested line and that this agent assumes responsibility for providing the line.
Also, driven in conjunction with HIT# to extend the snoop window.
HLOCK#
I
AGTL+
Host Lock: All system bus cycles sampled with the assertion of HLOCK# and
ADS#, until the negation of HLOCK# must be atomic, i.e. no hub interface or
AGP snoopable access to DRAM are allowed when HLOCK# is asserted by the
processor.
HREQ[4:0]#
I/O
AGTL+ 2x
Host Request Command: Defines the attributes of the request. In Enhanced
Mode HREQ[4:0]# are transferred at 2x rate. Asserted by the requesting agent
during both halves of Request Phase. In the first half the signals define the
transaction type to a level of detail that is sufficient to begin a snoop request. In the
second half the signals carry additional information to define the complete
transaction type.
The transactions supported by the MCH-M Host Bridge are defined in the Host
Interface section of this document.
HTRDY#
O
AGTL+
Host Target Ready: Indicates that the target of the processor transaction is able
to enter the data transfer phase.
RS[2:0]#
O
AGTL+
Response Status: Indicates type of response according to the following the table:
RS[2:0]
Response type
000
Idle state
001
Retry response
010
Deferred response
011
Reserved (not driven by MCH-M)
100
Hard Failure (not driven by MCH-M)
101
No data response
110
Implicit Write back
111
Normal data response
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