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參數(shù)資料
| 型號： | RG82870P2 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 126/157頁 |
| 文件大?。?/td> | 1407K |
| 代理商： | RG82870P2 |
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Intel
82845MP/82845MZ Chipset-Mobile (MCH-M)
70
Datasheet
250687-002
R
3.7.24.
ESMRAMC – Extended System Mgmt RAM Control Register –
Device #0
Address Offset:
9Eh
Default Value:
38h
Access:
Read Only, Read/Write, Read/Write Clear, Lock
Size:
8 bits
The Extended SMRAM register controls the configuration of Extended SMRAM space. The Extended
SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM memory space that is above 1
MByte.
Bit
Description
7
H_SMRAM_EN (H_SMRAME): Controls the SMM memory space location (i.e. above 1 MByte or
below 1 MByte) When G_SMRAME is 1 and H_SMRAME this bit is set to 1, the high SMRAM
memory space is enabled. SMRAM accesses from FEDA_0000h to FEDB_FFFFh are remapped to
DRAM address 000A0000h to 000BFFFFh.
Once D_LCK is set, this bit becomes read only.
6
E_SMRAM_ERR (E_SMERR): This bit is set when host accesses the defined memory ranges in
Extended SMRAM (High Memory and T-segment) while not in SMM space and with the D-OPEN bit =
0. It is software’s responsibility to clear this bit. The software must write a 1 to this bit to clear it
5
SMRAM_Cache (SM_CACHE): This bit is hardwired to ‘1’.
4
SMRAM_L1_EN (SM_L1): This bit is hardwired to ‘1’.
3
SMRAM_L2_EN (SM_L2): This bit is hardwired to ‘1’.
2:1
TSEG_SZ[1-0] (T_SZ): Selects the size of the TSEG memory block if enabled. This memory is
taken from the top of DRAM space (i.e. TOM - TSEG_SZ), which is no longer claimed by the memory
controller (all accesses to this space are sent to the hub interface if TSEG_EN is set). This field
decodes as follows:
TSEG_SZ[1,0]
Description
00
(TOM-128K) to TOM
01
(TOM-256K) to TOM
10
(TOM-512K) to TOM
11
(TOM-1M) to TOM (845MP Only)
Once D_LCK is set, this bit becomes read only.
0
TSEG_EN (T_EN): Enabling of SMRAM memory (TSEG, 128 Kbytes, 256 Kbytes, 512 Kbytes or 1
Mbytes of additional SMRAM memory) for Extended SMRAM space only. When G_SMRAME =1 and
TSEG_EN = 1, the TSEG is enabled to appear in the appropriate physical address space.
Once D_LCK is set, this bit becomes read only.
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