參數(shù)資料
型號(hào): RF5C296
廠商: RICOH COMPANY LTD
元件分類: 總線控制器
英文描述: TRI N PLUG F PLAS 4-20
中文描述: PCMCIA BUS CONTROLLER, PQFP144
封裝: 1.70 MM HEIGHT, PLASTIC, LQFP-144
文件頁數(shù): 53/93頁
文件大?。?/td> 449K
代理商: RF5C296
Notes for connecting to System bus except ISA bus
RF5C296/RF5C396L/RB5C396/RF5C396
49
The RF5C296 and the RF5C396 must be connected to any other system bus than the ISA bus in consideration of the fol-
lowing pins:
1) BALE Pin
The BALE pin signal is intended to latch the address signals output from the LA23 to LA17 pins because retention of
these pin signals is not guaranteed in the entire instruction cycle on the ISA bus. In practice,they are half-latched.
The BALE pin may be held at “H”, therefore, when the LA23 to LA17 pin signals are retained in the entire instruction
cycle on any other bus in the same manner as the SA16 to SA0
2) AEN Pin
The AEN pin signal indicates the DMA Mode when held at “H”. As such, it should be held at “L” when the DMA
Mode is not in use.
3) REFRESH# Pin
The REFRESH# pin signal indicates the refresh period of the ISA bus when held at “L”. For the RF5C296 and the
RF5C396, memory access is conditional upon the REFRESH# pin signal held at “H”. The REFRESH# pin signal
should be held at “H”, therefore, when not in use.
4) SYSCLK Pin
The SYSCLK pin signal normally has a frequency of 8.33MHz on the ISA bus. For the RF5C296 and the RF5C396,
the SYSCLK pin signal is used for the following five purposes :
· Determination of wait time
· Determination of the pulse width of the INTR# pin signal
· Determination of the reset pulse width of the card states change register in the explicit write back mode.
· Bit 0 function of Card Detect and General Control register.
· Determination of the high-level duration of the ZEROWS# and IOCHRDY pin signals
(For details, see “2.1 IOCS16#, MEMCS16#, ZEROWS#, and IOCHRDY Pins” in “2. Connections to System
Bus”.)
As long as the above purposes can be achieved, the SYSCLK pin signal may be available at a maximum frequency of
11MHz or in DC form.
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