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參數(shù)資料
| 型號(hào)： | RF3321 |
| 廠商： | RF MICRO DEVICES INC |
| 元件分類： | 衰減器 |
| 英文描述： | REVERSE PATH HIGH OUTPUT POWER PROGRAMMABLE GAIN AMPLIFIER |
| 中文描述： | 5 MHz - 65 MHz RF/MICROWAVE NARROW BAND LOW POWER AMPLIFIER |
| 封裝： | SSOP-16 |
| 文件頁(yè)數(shù)： | 4/16頁(yè) |
| 文件大?。?/td> | 195K |
| 代理商： | RF3321 |
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Preliminary
2-4
RF3321
Rev A10 010516
3
L
A
Serial Bus Block Diagram
Pin
1
Function
SHDNB
Description
Chip shutdown pin. Forcing a logic low causes all circuits to switch off
and gain settings to be lost.
Signal path enable pin. Logic high turns on signal path. Logic low turns
off signal path, but leaves serial bus active.
Not connected.
Interface Schematic
2
TX EN
3
4
NC
VIN
Input pin. This should be externally AC-coupled to signal source.
5
VINB
Complementary input pin. This should be externally coupled to signal
source. For single-ended use, this pin should be AC-coupled to ground.
This pin is connected to VCC1.
See pin 4.
6
7
8
9
10
11
12
VCC1
VCC1
RAMP
SCLK
CS
SDA
VOUTB
Same as pin 6.
External capacitor to ground controls start-up time.
Serial bus clock input.
Serial bus enable.
Serial bus data input.
Open collector output. Connect to VCC2 via balun primary.
13
14
15
16
PKG
BASE
VOUT
NC
NC
GND
GND
Open collector output. Connect to VCC2 via balun primary.
See pin 12.
Same as pin 3.
Same as pin 3.
Connect to ground.
Die is mounted on a heat sink slug that should be connected to ground.
Device grounds are internally bonded to the slug.
550
550
V
CC
500
500
V
INB
V
IN
300
V
OUT
V
OUTB
RE
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D0
D1
D2
D3
D4
D5
D6
POR
CS
SDA
SCLK
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| RF3321PCBA | 制造商:RFMD 制造商全稱:RF Micro Devices 功能描述:REVERSE PATH HIGH OUTPUT POWER PROGRAMMABLE GAIN AMPLIFIER |
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