參數資料
型號: RF3133PCBA
廠商: RF Monolithics, Inc.
英文描述: QUAD-BAND GSM850/GSM/DCS/PCS POWER AMP MODULE
中文描述: 四頻GSM850/GSM/DCS/PCS功率放大器模塊
文件頁數: 12/16頁
文件大?。?/td> 196K
代理商: RF3133PCBA
2-470
RF3133
Rev A4 030527
The switching transients due to low battery conditions are regulated by incorporating the following relationship limiting
the maximum V
RAMP
voltage (Equation 2). Although no compensation is required for typical battery conditions, the bat-
tery compensation required for extreme conditions is covered by the relationship in Equation 4. This should be added to
the terminal software.
(Eq. 4)
Note: Output power is limited by battery voltage. The relationship in Equation 4 does not limit output power. Equation 4
limits the V
RAMP
voltage to correspond with the battery voltage.
Due to reactive output matches, there are output power variations across frequency. There are a number of components
that can make the effects greater or less.
The components following the power amplifier often have insertion loss variation with respect to frequency. Usually, there
is some length of microstrip that follows the power amplifier. There is also a frequency response found in directional cou-
plers due to variation in the coupling factor over frequency, as well as the sensitivity of the detector diode. Since the
RF3133 does not use a directional coupler with a diode detector, these variations do not occur.
Input impedance variation is found in most GSM power amplifiers. This is due to a device phenomena where C
BE
and
C
CB
(C
GS
and C
SG
for a FET) vary over the bias voltage. The same principle used to make varactors is present in the
power amplifiers. The junction capacitance is a function of the bias across the junction. This produces input impedance
variations as the Vapc voltage is swept. Although this could present a problem with frequency pulling the transmit VCO
off frequency, most synthesizer designers use very wide loop bandwidths to quickly compensate for frequency variations
due to the load variations presented to the VCO.
The RF3133 presents a very constant load to the VCO. This is because all stages of the RF3133 are run at constant
bias. As a result, there is constant reactance at the base emitter and base collector junction of the input stage to the
power amplifier.
Noise power in PA's where output power is controlled by changing the bias voltage is often a problem when backing off of
output power. The reason is that the gain is changed in all stages and according to the noise formula (Equation 5),
(Eq. 5)
the noise figure depends on noise factor and gain in all stages. Because the bias point of the RF3133 is kept constant
the gain in the first stage is always high and the overall noise power is not increased when decreasing output power.
Power control loop stability often presents many challenges to transmitter design. Designing a proper power control loop
involves trade-offs affecting stability, transient spectrum and burst timing.
In conventional architectures the PA gain (dB/ V) varies across different power levels, and as a result the loop bandwidth
also varies. With some power amplifiers it is possible for the PA gain (control slope) to change from 100dB/V to as high
as 1000dB/V. The challenge in this scenario is keeping the loop bandwidth wide enough to meet the burst mask at low
slope regions which often causes instability at high slope regions.
The RF3133 loop bandwidth is determined by internal bandwidth and the RF output load and does not change with
respect to power levels. This makes it easier to maintain loop stability with a high bandwidth loop since the bias voltage
and collector voltage do not vary.
An often overlooked problem in PA control loops is that a delay not only decreases loop stability it also affects the burst
timing when, for instance the input power from the VCO decreases (or increases) with respect to temperature or supply
voltage. The burst timing then appears to shift to the right especially at low power levels. The RF3133 is insensitive to a
change in input power and the burst timing is constant and requires no software compensation.
V
RAMP
3
8
V
BATT
0.18
+
F
TOT
F
1
----2
1
G
1
G
1
G
2
1
------3
+
+
=
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參數描述
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