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參數(shù)資料
| 型號： | RD28F6408W30T85 |
| 廠商： | INTEL CORP |
| 元件分類： | 存儲器 |
| 英文描述： | 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30) |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA80 |
| 封裝： | 14 X 8 MM, 0.80 MM PITCH, STACK, CSP-80 |
| 文件頁數(shù)： | 11/82頁 |
| 文件大?。?/td> | 749K |
| 代理商： | RD28F6408W30T85 |
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28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Preliminary
5
2.4
Signal Descriptions
Table 2. Signal Descriptions (Sheet 1 of 2)
Symbol
Type
Name and Function
A
25
–
0
I
ADDRESS:
Device address. Addresses are internally latched during read and write cycles.
32-Mbit flash: A
20
–
0
; 64-Mbit flash: A
21
–
0
; 128-Mbit flash: A
22
–
0
; 4-Mbit SRAM: A
17
–
0
; 8-Mbit SRAM: A
18
–
0
DQ
15
–
0
I/O
DATA INPUT/OUTPUTS:
Inputs data and commands during write cycles, outputs data during query, id
reads, memory, status register, protection register, and configuration code reads. Data signals float when
the chip or outputs are deselected. Data is internally latched during writes. Query accesses and status
register accesses use DQ
0
–
DQ
7
. All other accesses use DQ
0
–
DQ
15
.
ADV#
I
FLASH ADDRESS VALID:
Internally latches addresses. In page mode, addresses are internally latched on
the rising edge of ADV#. In burst mode, address internally latched on the rising edge of ADV# or rising/
falling edge of CLK, whichever occurs first. Connect ADV# to GND when the flash device is operating in
asynchronous mode only.
CE#
I
FLASH CHIP ENABLE:
Enables/disables flash device. CE#-low enables the device. CE#-high disables the
device and places the device into standby mode. CE# high places data and WAIT signals at a High-Z level.
S-CS
1
#
I
SRAM CHIP SELECT1:
Activates the SRAM internal control logic, input buffers, decoders and sense
amplifiers. S-CS
1
# is active low. S-CS
1
# high deselects the SRAM memory device and reduces power
consumption to standby levels.
S-CS
2
I
SRAM CHIP SELECT2:
Activates the SRAM internal control logic, input buffers, decoders and sense
amplifiers. S-CS
2
is active high. S-CS
2
low deselects the SRAM memory device and reduces power
consumption to standby levels.
CLK
I
FLASH CLOCK:
Synchronizes the device to the system bus frequency. (Used only in burst mode.)
OE#
I
FLASH OUTPUT ENABLE:
Enables/disables device output buffers. OE# low enables the device output
buffers. OE# high disables the device output buffers and places all outputs at a High-Z level.
S-OE#
I
SRAM OUTPUT ENABLE:
Activates the SRAM outputs through the data buffers during a read operation.
S-OE# is active low.
RST#
I
FLASH RESET:
Enables/disables device operation. RST# low initializes internal circuitry and disables
device operation. RST# high enables device operation.
WAIT
O
FLASH WAIT:
Indicates valid data in burst read mode. WAIT is at High-Z until the configuration register bit
CR.10 is set, which also determines its polarity when asserted.
WE#
I
FLASH WRITE ENABLE:
Enables/disables device write buffers. WE# low enables the device write buffers.
Data is latched on the rising edge of WE#. WE# high disables the device write buffers.
S-WE#
I
SRAM WRITE ENABLE:
Controls writes to the SRAM memory array. S-WE# is active low.
S-UB#
I
SRAM UPPER BYTE ENABLE:
Enables the upper bytes for SRAM (DQ
15-8
). S-UB# is active low. S-UB#
and S-LB# must be tied together to restrict x16 mode.
S-LB#
I
SRAM LOWER BYTE ENABLE:
Enables the lower bytes for SRAM (DQ
7-0
). S-LB# is active low. S-UB#
and S-LB# must be tied together to restrict x16 mode.
WP#
I
FLASH WRITE PROTECT:
Enables/disables the device lock-down function. WP# low enables the lock-
down mechanism and blocks marked lock-down cannot be unlocked by system software. WP# high
disables the lock-down mechanism and blocks marked lock-down can be unlocked by system software.
V
PP
Pwr
FLASH PROGRAM/ERASE POWER:
Hardware erase and program protection. A valid V
PP
voltage on this
ball allows erase or programming. Memory contents cannot be altered when V
PP
< V
PPLK
. Block erase and
program at invalid V
PP
voltages should not be attempted. Set V
PP
= V
CC
for in-system read, program, and
erase operations. V
PP
must remain above V
PP1
Min to perform in-system operations. V
PP2
can be applied to
main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles.
V
PP
can be V
PP2
for a
cumulative total, not to exceed 80 hours maximum. Extended use of this ball at V
PP2
may reduce block
cycling capability.
V
CC
Pwr
FLASH POWER SUPPLY:
Flash operations at invalid V
CC
voltages should not be attempted.
V
CCQ
Pwr
FLASH OUTPUT POWER SUPPLY:
Enables all input and output signals to be driven at V
CCQ
.
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