參數(shù)資料
型號： RD28F1604C3T90
廠商： INTEL CORP
元件分類： 存儲器
英文描述： 3 VOLT INTEL Advanced+BootBlock FlashMemory(C3)Stacked-ChipScalPackageFamilye
中文描述： SPECIALTY MEMORY CIRCUIT, PBGA66
封裝： 8 X 10 MM, 1.20 MM HEIGHT, SCSP-66
文件頁數(shù)： 9/70頁
文件大?。?/td> 1223K
代理商： RD28F1604C3T90
3VoltIntel
Advanced+BootBlockFlashMemoryStacked-CSPFamily
Datasheet
9
2. TomaintaincompatibilitywithallJEDECVariationBoptionsforthisballlocationC6,thisC6landpadshould
beconnecteddirectlytothelandpadforballG4(A17).
1.4
SignalDefinitions
Table2.definesthesignaldefinitionsshowninthepreviousballout.
Table2. 3VoltIntel
Advanced+BootBlockStacked-CSPBallDescriptions(Sheet1of2)
Symbol
Type
NameandFunction
A[20:0]
INPUT
ADDRESSINPUTS
formemoryaddresses.Addressesareinternallylatchedduringaprogramor
erasecycle.
2-Mbit:A[16:0]
4-Mbit:A[18:0]
16-Mbit:A[19:0]
32-MbitA[20:0]
DQ[15:0]
INPUT/
OUTPUT
DATAINPUTS/OUTPUTS:
InputsarraydataforSRAMwriteoperationsandonthesecondF-CE#
andF-WE#cycleduringaflashprogramcommand.Inputscommandstotheflash’sCommand
UserInterfacewhenF-CE#andF-WE#areasserted.Dataisinternallylatched.Outputsarray,
configurationandstatusregisterdata.Thedataballsfloattotri-statewhenthechipisde-selected
ortheoutputsaredisabled.
F-CE#
INPUT
FLASHCHIPENABLE:
Activatestheflashinternalcontrollogic,inputbuffers,decodersand
senseamplifiers.F-CE#isactivelow.F-CE#highde-selectstheflashmemorydeviceandreduces
powerconsumptiontostandbylevels.
S-CS1#
INPUT
SRAMCHIPSELECT1:
ActivatestheSRAMinternalcontrollogic,inputbuffers,decodersand
senseamplifiers.S-CS1#isactivelow.S-CS1#highde-selectstheSRAMmemorydeviceand
reducespowerconsumptiontostandbylevels.
S-CS2
INPUT
SRAMCHIPSELECT2:
ActivatestheSRAMinternalcontrollogic,inputbuffers,decodersand
senseamplifiers.S-CS2isactivehigh.S-CS2lowde-selectstheSRAMmemorydeviceand
reducespowerconsumptiontostandbylevels.
F-OE#
INPUT
FLASHOUTPUTENABLE:
Enablesflash’soutputsthroughthedatabuffersduringaread
operation.F-OE#isactivelow.
S-OE#
INPUT
SRAMOUTPUTENABLE:
EnablesSRAM’soutputsthroughthedatabuffersduringaread
operation.S-OE#isactivelow.
F-WE#
INPUT
FLASHWRITEENABLE:
Controlswritestoflash’scommandregisterandmemoryarray.F-WE#
isactivelow.AddressesanddataarelatchedontherisingedgeofthesecondF-WE#pulse.
S-WE#
INPUT
SRAMWRITEENABLE:
ControlswritestotheSRAMmemoryarray.S-WE#isactivelow.
S-UB#
INPUT
SRAMUPPERBYTEENABLE:
EnablestheupperbyteforSRAM(DQ
8
–DQ
15
).
S-UB#isactivelow.
S-LB#
INPUT
SRAMLOWERBYTEENABLE:
EnablesthelowerbyteforSRAM(DQ
0
–DQ
7
).
S-LB#isactivelow.
F-RP#
INPUT
FLASHRESET/DEEPPOWER-DOWN:
Usestwovoltagelevels(V
IL
,V
IH
)tocontrolreset/deep
power-downmode.
WhenF-RP#isatlogiclow,thedeviceisinreset/deeppower-downmode
,whichdrivesthe
outputstoHigh-Z,resetstheWriteStateMachine,andminimizescurrentlevels(I
CCD
).
WhenF-RP#isatlogichigh,thedeviceisinstandardoperation
.WhenF-RP#transitionsfrom
logic-lowtologic-high,thedeviceresetsallblockstolockedanddefaultstothereadarraymode.
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