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參數(shù)資料
| 型號： | RD-19230FG-203 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, PQFP64 |
| 封裝： | 0.520 X 0.520 INCH, GREEN, PLASTIC, QFP-64 |
| 文件頁數(shù)： | 21/23頁 |
| 文件大?。?/td> | 476K |
| 代理商： | RD-19230FG-203 |
FIGURE 5. -5V INVERTER CONNECTIONS
17
25
22
16
23
24
26
27
58
33
+
10
μF/10V
VDD
VDDP
PCAP
+5V
NCAP
GND
AGND
VSSP
VSS *
VSS
RD-19230
47
μF/10V
* Pin 16 has been renamed Vss since it will typically be connected to
-5 VDC. Applications requiring a differential front-end configuration
must connect this pin to Vss. Voltage follower mode should also be implemented
with pin 16 tied to Vss by making external connections between the output
of the SIN/COS amplifiers and their respective inputs. When left unconnected,
the RD-19230 will internally configure the front-end amplifiers in voltage
follower mode.
GND
+
47
μF
7
Data Device Corporation
www.ddc-web.com
RD-19230
W-05/08-0
4) This device has several high impedance amplifier inputs
(+C, -C, +S, -S, -VCO, VEL SJ1, and VEL SJ2) that are sensi-
tive to noise coupling. External components should be con-
nected as close to the converter as possible.
5) Setup of bandwidth and velocity scaling for the optimized crit-
ically damped case example as follows:
DDC has external component selection software which con-
siders all the criteria below and, in a simple fashion, asks the
key parameters (carrier frequency, resolution, bandwidth, and
tracking rate) to derive the external component values.
As an example:
Calculate component values for a 16-bit converter with 100Hz band-
width, a tracking rate of 10 RPS and a full scale velocity of 4 Volts.
Note: DDC has software available to perform the previous calcu-
lation. Contact DDC to request software or visit our web site at
www.ddc-we.com to download software.
HIGHER TRACKING RATES AND CARRIER
FREQUENCIES
Maximum tracking rate is limited by the velocity voltage satura-
tion (nominally 4 V) and the maximum internal clock rate (nomi-
nally 1,333,333 Hz for R CLK = 30k). To achieve higher tracking
- Rv =
= 97655
Ω
- Compute CBW (pF) =
= 21955 pF
- Compute RB =
= 410 k
Ω
4 V
10 rps x 216 x 50 pF x 1.25 V
0.9
21955 x 10 -12 x 100 Hz
3.2 x 67 kHz x 108
97655 x 100 Hz2
- Select the desired f BW (closed loop) based on overall
system dynamics.
- Select f carrier
≥ 3.5f BW
- Select the applications tracking rate (in accordance with TABLE 3),
and use appropriate values for R SET and R CLK
- Compute Rv =
- Compute CBW (pF) =
- Where Fs = 67 kHz for R CLK = 30 K
Ω
100 kHz for R CLK = 20 K
Ω
125 kHz for R CLK = 15 K
Ω
- Compute RB =
- Compute
3.2 x Fs (Hz) x 108
Rv x (f BW)2
Full Scale Velocity Voltage
Tracking Rate (rps) x 2 resolution x 50 pF x 1.25 V
0.9
CBW x f BW
CBW
10
- ( FS = Internal Sample Frequency )
rates, a higher internal counting rate must be programmed by
setting RCLK to a value less than 30k. See TABLE 4 for the
appropriate values.
Select frequency/resolution from TABLE 4 then reference TABLE
3 for max tracking rate. The Rv resistor and an internal 50pF
capacitor are configured as an integrating circuit that resets to
zero after a count occurs in either direction. This circuit acts as a
VCO with velocity as its input and CB as its output. The Rv resis-
tor and an internal 50pF capacitor determine the maximum rate
of the VCO. Rv must be chosen such that the maximum rate of
the VCO is less than the maximum internal clock rate. Choose
the tracking rate in accordance with TABLE 3 to insure this rela-
tionship. The rates shown in TABLE 3 are based on ~90% of the
nominal internal clock rate.
The relationship between the velocity voltage and the VCO rate
is given by:
Velocity Voltage
VCO Frequency
1
(Rv x 50 pF x 1.25)
=
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