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RC7105
PRODUCT SPECIFICATION
8
A
Table 2. Data Bytes 0-2 Serial Configuration Map
Note:
At power up all SDRAM outputs are enabled and active. Program all reserved bits to a”0”.
Bit(s)
Data Byte 0 SDRAM Active/Inactive Register (1=Enable, 0=Disable)
7
11
SDRAM5
6
10
SDRAM4
5
N/A
Reserved
4
N/A
Reserved
3
7
SDRAM3
2
6
SDRAM2
1
3
SDRAM1
0
2
SDRAM0
Data Byte 1 SDRAM Active/Inactive Register (1=Enable, 0=Disable)
7
27
SDRAM11
6
26
SDRAM10
5
23
SDRAM9
4
22
SDRAM8
3
N/A
Reserved
2
N/A
Reserved
1
19
SDRAM7
0
18
SDRAM6
Data Byte 2 SDRAM Active/Inactive Register (1=Enable, 0=Disable)
7
N/A
Reserved
6
12
SDRAM12
5
N/A
Reserved
4
N/A
Reserved
3
N/A
Reserved
2
N/A
Reserved
1
N/A
Reserved
0
N/A
Reserved
Affected Pin
Pin No.
Bit Control
Pin Name
Control Function
0
1
Clock Output Disable
Clock Output Disable
(Reserved)
(Reserved)
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Low
Low
—
—
Low
Low
Low
Low
Active
Active
—
—
Active
Active
Active
Active
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
(Reserved)
(Reserved)
Clock Output Disable
Clock Output Disable
Low
Low
Low
Low
—
—
Low
Low
Active
Active
Active
Active
—
—
Active
Active
(Reserved)
Clock Output Disable
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
—
Low
—
—
—
—
—
—
—
Active
—
—
—
—
—
—
Writing Data Bytes
Each bit of the 10 data bytes controls a particular device
function within the RC7105. Bit 7, the MSB, is written first.
See Table 2 for bit descriptions of Data Bytes 0–2.