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PRODUCT SPECIFICATION
RC5040
17
PCB Layout Guidelines and
Considerations
PCB Layout Guidelines
1.
Placement of the MOSFETs relative to the RC5040 is
critical. The MOSFETs (M1 & M2), should be placed
such that the trace length of the HIDRV pin from the
RC5040 to the FET gates is minimized. A long lead
length on this pin will cause high amounts of ringing due
to the inductance of the trace combined with the large
gate capacitance of the FET. This noise will radiate all
over the board, and because it is switching at such a high
voltage and frequency, it will be very difficult to sup-
press.
Figure 9 below depicts an example of good placement
for the MOSFETs in relation to the RC5040
and also an example of problematic placement for the
MOSFETs.
In general, all of the noisy switching lines should be kept
away from the quiet analog section of the RC5040. That
is to say, traces that connect to pins 12 and 13 (HIDRV
and VCCQP) should be kept far away from the traces
that connect to pins 1 through 5, and pin 16.
2.
Place decoupling capacitors (.1
m
F) as close to the
RC5040 pins as possible. Extra lead length on these will
negate their ability to suppress noise.
3.
Each VCC and GND pin should have its own via down
to the appropriate plane underneath. This will help give
isolation between pins.
4.
Surround the CEXT timing capacitor with a ground
trace as much as possible. Also be sure to keep a ground
or power plane underneath the capacitor for further noise
isolation. This will help to shield the oscillator pin 1
from the noise on the PCB. Place this capacitor as close
to the RC5040 pin 1 as possible.
5.
Place MOSFETs, inductor and Schottky as close
together as possible for the same reasons as #1 above.
Place the input bulk capacitors as close to the drains of
MOSFETs as possible. In addition, placement of a
0.1
m
F decoupling cap right on the drain of each MOS-
FET will help to suppress some of the high frequency
switching noise on the input of the DC-DC converter.
6.
The traces that run from the RC5040 IFB (pin 4) and
VFB (pin 5) pins should be run together next to each
other and be Kelvin connected to the sense resistor. Run-
ning these lines together will help in rejecting some of
the common noise that is presented to the RC5040 feed-
back input. Try as much as possible to run the noisy
switching signals (HIDRV & VCCQP) on one layer; and
use the inner layers for only power and ground. If the top
layer is being used to route all of the noisy switching
signals, use the bottom layer to route the analog sensing
signals VFB and IFB.
Figure 9. MOSFET Layout Guidelines
Correct layout
8
7
6
2
11
15
RC5040
RC5040
14
13
12
3
16
1
5
4
Poor layout
“Quiet” Pins
=
9
10
17
18
19
20
8
7
6
2
11
15
14
13
12
3
16
1
5
4
9
10
17
18
19
20
65-5040-17