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PRODUCT SPECIFICATION
RC5031
11
P
Inductor and Schottky Diode Placement
The inductor and fly-back Schottky diode need to be placed
close to the source of the power MOSFET for the same rea-
sons stated above. The node connecting the inductor and
Schottky diode will swing between the drain voltage of the
FET and the forward voltage of the Schottky diode. It is rec-
ommended that this node be converted to a plane if possible.
This node will be part of the high current path in the design,
and as such it is best treated as a plane in order to minimize
the parasitic resistance and inductance on that node. Since
most PC board manufacturers utilize 1/2 oz copper on the
top and bottom signal layers of the PCB, it is not recom-
mended to use these layers to rout the high current portions
of the regulator design. Since it is more common to use 1 oz.
copper on the PCB inner layers, it is recommended to use
those layers to route the high current paths in the design.
Capacitor Placement
One of the keys to a successful switch-mode power supply
design is correct placement of the low ESR capacitors.
Decoupling capacitors serve two purposes; first there must
be enough bulk capacitance to support the expected transient
current of the CPU, and second, there must be a variety of
values and capacitor types to provide noise supression over a
wide range of frequencies. The low ESR capacitors on the
input side (5V) of the FET must be located close to the drain
of the power FET. Minimizing parasitic inductance and
resistance is critical in supressing the ringing and noise
spikes on the power supply. The output low ESR capacitors
need to be placed close to the output sense resistor to provide
good decoupling at the voltage sense point. One of the
characteristics of good low ESR capacitors is that the imped-
ance gradually increases as the frequency increases. Thus for
high frequency noise supression, good quality low induc-
tance ceramic capacitors need to be placed in parallel with
the low ESR bulk capacitors. These can usually be 0.1
m
F
1206 surface mount capacitors.
Power and Ground Connections
The connection of VCCA to the 5V power supply plane
should be short and bypassed with a 0.1
m
F directly at the
VCCA pin of the RC5031. The ideal connection would be a
via down to the 5V power plane. A similar arrangement
should be made for the VCCL pin that connects to +12V,
though this one is somewhat less critical since it powers only
the linear op-amp. Each ground should have a separate via
connection to the ground plane below.
A 12V power supply is used to bias the VCCP. A 47
W
resistor is used to limit the transient current into VCCP.
A 1uF capacitor filter is used to filter the VCCP supply and
source the transient current required to charge the MOSFET
gate capacitance. This method provides sufficiently high
gate bias voltage to the MOSFET (V
GS
), and therefore
reduces R
DS(ON)
of the MOSFET and its power loss.
Figure 13 provides about 5V of gate bias which works well
when using typical logic-level MOSFETs, as shown in
Figure 14. Non-logic-level MOSFETs should not be used
because of their higher R
DS(ON)
.
MOSFET Gate Bias
Figure 13. 12V Gate Bias Configuration
+5V
47
W
VO
R
SENSE
L1
DS1
GNDP
M1
+12V
C
BULK
SDRV
VCCP
1uF
Figure 12. Examples of good and poor layouts
Example of
a Good layout
10
11
12
9
8
7
6
5
4
2
1
15
16
14
13
3
10
11
12
9
8
7
6
5
4
2
1
15
16
14
13
3
Example of
a Problem layout
SDRV
SWDRV
VREF
IFBL
IFBH
VREF
quiet pins
and trace is
rquiet pins and
ktrace length is
“Quiet” Pins
=
CEXT
CEXT
too long.