參數(shù)資料
型號(hào)： RC64474
廠商： Integrated Device Technology, Inc.
英文描述： RISControllerTM Embedded 64-bit Microprocessor, based on RISCore4000
中文描述： RISControllerTM嵌入式64位的基礎(chǔ)上RISCore4000微處理器，
文件頁(yè)數(shù)： 4/25頁(yè)
文件大?。?/td> 403K
代理商： RC64474
4 of 25
April 10, 2001
RC64474 RC64475
Table 2 RC64474/RC64475 Instruction/Data Cache Attributes
S ystem Interfac es
The RC64475 supports a 64-bit systeminterface that is bus compat-
ible with the RC4650 and RC64575 systeminterface. The systeminter-
face consists of a 64-bit Address/Data bus with 8 check bits and a 9-bit
command bus that is parity protected.
During 64-bit operation, RC64475 systemaddress/data (SysAD)
transfers are protected with an 8-bit parity check bus, SysADC. When
initialized for 32-bit operation, the RC64475’s SysAD can be viewed as a
32-bit multiplexed bus that is protected by 4 parity check bits.
The RC64474 supports a 32-bit systeminterface that is bus compat-
ible with the RC4640. During 32-bit operation, SysAD transfers are
performed on a 32-bit multiplexed bus (SysAD 31:0) that is protected by
4 parity check bits (SysADC 6:0).
Writes to external memory—whether they are cache mss write-
backs, stores to uncached or write-through addresses—use the on-chip
write buffer
. The write buffer holds a maximumof four 64-bit addresses
and 64-bit data pairs. The entire buffer is used for a data cache write-
back and allows the processor to proceed in parallel with memory
updates.
Included in the systeminterface are
six handshake signals
:
RdRdy* WrRdy* ExtRqst* Release* ValidOut* and ValidIn*
six inter-
rupt inputs,
and a
simple timing
specification that is capable of trans-
ferring data between the processor and memory at a peak rate of
1000MB/sec. A boot-time selectable option to run the systeminterface
as 32-bits wide—using basically the same protocols as the 64-bit
system—is also supported.
Charac teristic s
Instruc tion
Data
Size
16KB
16KB
Organization
2-way set
associative
2-way set
associative
Line size
32B
32B
read unit
32-bits
64-bits
write policy
na
write-back, write-through
with or without write-allocate
Line transfer order
sub-block order,
for refill
sub-block order, for load
sequential order, for store
Mss restart
after transfer of:
entire line
mss word
Parity
per-word
per-byte
Cache locking
per set
per set
A
boot-time mode control interface
initializes fundamental
processor modes. The boot-time mode control interface is a serial inter-
face that operates at a very low frequency (MasterClock divided by
256). This low-frequency operation allows the initialization information to
be kept in a low-cost EPROM; alternatively, the twenty-or-so bits could
be generated by the systeminterface ASIC or a simple PAL. The boot-
time serial streamand configuration options are listed in Table 3.
The
clocking interface
allows the CPU to be easily mated with
external reference clocks. The CPU input clock is the bus reference
clock and can be between 25 and 125MHz. An on-chip
phase-locked-
loop (PLL)
generates the pipeline clock (PClock) through multiplication
of the systeminterface clock by values of 2,3,4,5,6,7 or 8, as defined at
systemreset. This allows the pipeline clock to be implemented at a
significantly higher frequency than the systeminterface clock. The
RC64474/475 support single data (one to eight bytes) and 8-word block
transfers on the SysAD bus.
The RC64474/475 implement additional
write protocols
that
double the effective write bandwidth
. The write re-issue has a repeat
rate of 2 cycles per write. Pipelined writes have the same 2-cycle per
write repeat rate, but can issue an additional write after WrRdy*de-
asserts.
Choosing a 32- or 64-bit wide systeminterface dictates whether a
cache line block transaction requires 4 double word data cycles or 8
single word cycles as well as whether a single data transfer—larger than
4 bytes—must be divided into two smaller transfers.
Board-level testing
during Run-Time mode is facilitated through the
full JTAG boundary scan facility. Six pins—TDI, TDO, TMS, TCK, TRST*
and JTAG32*—have been incorporated to support the standard JTAG
interface.
S ystem Enhanc ement
To facilitate discrete
interface to SDRAM
, the RC64474/475 bus
interface is enhanced during write cycles with a programmable delay
that is inserted between the write address and the write data (for both
block and non-block writes).
The bus delay can be defined as 0 to 7 MasterClock cycles and is
activated and controlled through mode bit (17:15) settings selected
during the reset initialization sequence. The ‘000’ setting provides the
same write operations timng protocol as the RC4640, RC4650, and
RC5000 processors.
相關(guān)PDF資料
PDF描述
RC64475 RISControllerTM Embedded 64-bit Microprocessor, based on RISCore4000
RC6704 Triple Fixed Gain Video Amplifier
RC7106 133MHz Spread Spectrum Clock for Motherboards
RC7151 VOLTAGE-TO-FREQUENCY CONVERTER
RC7151PC VOLTAGE-TO-FREQUENCY CONVERTER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
RC64475 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:RISControllerTM Embedded 64-bit Microprocessor, based on RISCore4000
RC645024 制造商:TE Connectivity 功能描述: 制造商:TE Connectivity / Schrack Brand 功能描述:
RC65 制造商:Distributed By MCM 功能描述:DirecTV Replacement Remote 制造商:MCM 功能描述:DIRECTV REPLACEMENT REMOTE 64KB MEMORY RC65X
RC6500LP 制造商:AGERE 功能描述:6500LPB2-RS-D 制造商:AGERE 功能描述:6500LPD-RS-D 制造商:AGERE 功能描述:6500LPD-XF-D 制造商:AGERE 功能描述:6500LPB2-XF-D
RC6505 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Differential IF Front-End
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*