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參數(shù)資料
| 型號： | RC64474 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | RISControllerTM Embedded 64-bit Microprocessor, based on RISCore4000 |
| 中文描述： | RISControllerTM嵌入式64位的基礎(chǔ)上RISCore4000微處理器， |
| 文件頁數(shù)： | 17/25頁 |
| 文件大?。?/td> | 403K |
| 代理商： | RC64474 |
17 of 25
April 10, 2001
RC64474 RC64475
Capac itive Load Deration—RC64474/RC64475
S ystem Interface Parameters
Note:
Operation of the RC64474/RC64475 is only guaranteed with the Phase Lock Loop enabled.
Boot-T ime Interfac e Parameters
Parameter
S ymbol
Test
Conditions
180MHz
200MHz
250MHz
Units
Min
Max
Min
Max
Min
Max
Load Derate
C
LD
—
—
2
—
2
—
2
ns/25pF
Parameter
1
1.
Timngs are measured from1.5V of the clock to 1.5V of the signal.
2.
Capacitive load for all output timngs is 50pF.
3.
Guaranteed by design.
4.
50pf loading on external output signals, fastest settings. Also applies to JTAG signals (TRST*TDO,TDI,TMS)
S ymbol
Test Conditions
RC64474/
RC64475
180MHz
RC64474/
RC64475
200MHz
RC64474/
RC64475
250MHz
Units
Min
Max
Min
Max
Min
Max
Data Output
2
t
DM
= Min
t
DO
= Max
mode
14..13
= 10
mode
14..13
= 11
mode
14..13
= 00
mode
14..13
= 01
mode
14..13
= 10
mode
14..13
= 11
mode
14..13
= 00
mode
14..13
= 01
t
rise
= 5ns
t
fall
= 5ns
0
3
6
0
3
5
0
3
4.7
ns
0
3
6
0
3
5
0
3
4.7
ns
—
9
—
9
—
7
ns
—
9
—
9
—
7
ns
Data Output Hold
t
DOH4
0
3
—
0
3
—
0
3
—
ns
0
3
—
0
3
—
0
3
—
ns
0
3
—
0
3
—
0
3
—
ns
0
3
—
0
3
—
0
3
—
ns
Input Data Setup
t
DS
2
—
2
—
2
—
ns
Input Data Hold
t
DH
1.0
—
1.0
—
1.0
—
ns
Parameter
S ymbol
RC64474/
RC64475
180 MHz
RC64474/
RC64475
200 MHz
RC64474/
RC64475
250MHz
Units
Min
Max
Min
Max
Min
Max
Mode Data Setup
t
DS
3
—
3
—
3
—
Master Clock Cycle
Mode Data Hold
t
DH
0
—
0
—
0
—
Master Clock Cycle
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