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RC5060
11
P
It is important to note that the softstart pin is not an enable;
pulling it low will not necessarily turn off all outputs.
Charge Pump
In main power operation, the RC5060 is run from the +12V
main supply. This supply also provides voltage to the various
MOSFET gates. However, during standby, this supply is off.
To provide power to the chip and the appropriate gates, the
RC5060 incorporates a free-running charge pump. As shown
in Figures 3 and 4, and in the block diagram on the front
page, a capacitor attached between pins 1 and 2 of the RC5060
acts as a charge pump with internal diodes. The charge pump
output is internally diode or’red with the 12V input. The 12V
input must have a series diode to prevent back-feeding the
charge pump to the + 12V main when in standby. The 12V
input line needs a bypass capacitor for high-frequency noise
rejection.
Overcurrent
The RC5060 does not directly detect current through the
eight devices that power its outputs. Instead, it monitors the
four output voltages. In the event of a hard short, the voltage
drops below 80% of nominal, and all outputs are latched off,
and remain off until 5V standby power is recycled. The over-
current latch off is delayed by 30μsec to prevent nuisance trips.
During softstart, the overcurrent voltage monitors are kept
proportional to the reference, to avoid tripping overcurrent
during startup. The monitors are kept active during softstart,
to avoid turning on into a short.
In the S5 state, when the memory outputs are off, the voltage
monitors on the memory lines are disabled, to prevent trip-
ping the overcurrent. When turning these lines back on from
the S5 state, the delay prevents overcurrent from tripping.
If the 2.5V dual is not used, its feedback line, pin 15, must be
connected to 5V dual as shown in Figure 4, to prevent an
overcurrent trip.
UVLO
If the +5V standby is below approximately 4.5V, the RC5060
will leave off or turn off all outputs. Similar comments apply
to the +12V main at 7.5V. The +5V standby UVLO has
approximately 0.5V hysteresis, the +12V main UVLO 1V.
Power Good
The Power Good is an open collector that pulls low if any of
the outputs are less than 80% of nominal.
Over Temperature
The RC5060 is capable of sourcing substantial current, 200mA
minimum to the RAMBUS transistor’s base during S0, 144mA
to the RAMBUS line during S3, and 100mA to SDRAM
during S3. As a result, there can be heavy power dissipation
in the IC. While the RC5060 is designed to accept this power
dissipation, any overloading of outputs can cause excessive
heating. If the RC5060 die temperature exceeds about 150°,
all outputs are shut off. Outputs remain off until the die tem-
perature returns to its safe area.
Transistor Selection
External transistor selection depends on usage, differing for
the linear regulators and the switches.
The MOSFET switches, Ql, Q3, Q5 and Q6 should be sized
based on regulation requirements and power dissipation.
Since the ATX outputs are ±5%, the outputs driven from
them must be wider. As an example, if we want to hold 3.3V
SDRAM to -10%, we can drop only 5% = 165mV across Q1.
At 4.8A, this means Ql must have a maximum R
DS,on
of
165mV/4.8A = 34m
, including tolerance and self-heating
effects. We thus choose a Fairchild FDS4410Y, which has
20m
maximum R
DS, on
at 4.5V V
GS
at 25°C. We can esti-
mate power dissipation as (4.8A)
2
* 20m
= 460mW, which
should be acceptable for this package. Similar calculations
apply to the other MOSFET switches.
Q4 is a MOSFET functioning as a linear regulator. Since it
delivers only 500mA, it is easy to select a MOSFET, it need
only have R
DS,on
less than (5V–5%–3.3V)/500mA = 2.9
.
We select the Fairchild NDS9956A which has maximum
R
DS, on
of 110m
at 4.5V V
2
at 25°C. Power dissipation
will be a maximum of (0.5A)
* 110m
= 27mW.
Q2 is an NPN bipolar functioning as a linear regulator. As
already discussed, it must have a V
CE,sat
lower than 635mV
at I
E
= 2A and I
B
= 200mA. Its power dissipation can be as
high as (3.3V + 5%–2.5V) * 2A = l.9W.
Output Capacitor Selection
Output capacitor selection depends on whether the line has
overlap time or not.
For both the 5V dual and the 2.5V dual, there is guaranteed
overlap time between when one source is turned on and the
other source turned off. For these outputs, the output capaci-
tor is not needed to hold up the supply, but only for noise fil-
tering and to respond to transient loading.
The 3.3V dual and 3.3V SDRAM outputs have deadtime
between when one source is turned off and the other source
turned on. During the time when both are off, the output cur-
rent must be supplied by the output capacitor. Mitigating
this, it must be realized that the system will be designed in
such a way that the current has gone to its sleep value before
the transition occurs. For example, the 3.3V dual has a sleep
current of 500mA maximum. Maximum deadtime is 6μsec,
and so charge depletion is 500mA * 6μsec = 3μC. Suppose
that we have a total of 8% drop due to the source tolerance
and the MOSFET drop, and we are trying to hold 10% regu-
lation. The remaining 2% = 66mV implies a minimum
capacitance of 3μC/66mV = 45μF.