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RC7315
PRODUCT SPECIFICATION
2
Pin Assignments
28-Pin PLCC
(Top View)
V
EE
V
SRCA
NC
V
CCO
V
EEO
V
EE
V
INH+
INH-
V
IN+
V
IN-
C
VOH
V
EE
V
E
V
L
N
T
V
H
C
V
V
E
V
E
S
V
C
G
N
N
V
E
1
5
6
7
8
9
10
11
25
24
23
22
21
20
19
2
3
4
282726
14 15
13
12
16 1718
Pin Description
Name
C
VOL
C
VOH
Pin Number
17
Function
Bypass capacitor for V
bypassed to the ground plane with a 1,000 pF chip capacitor placed as close to the pin
as possible.
Chip ground
. Should be connected to the printed circuit board’s ground plane at the
pin.
Differential digital inputs
. When INH is true (i.e. INH+ > INH-) the driver is forced into
the high impedance state. Although these inputs are normally driven by ECL signals,
they have a wide enough common mode range that any one of the inputs may be
driven by a TTL or CMOS signal provided that the other input is tied to the appropriate
threshold voltage.
Slew rate control for both edges
. Slew rate of both rising and falling edges decreases
as the control current is changed from 0 mA to -0.5 mA. SRC can be programmed with
a current DAC or set to a fixed value using a resistor.
Increases the speed of the falling edge to match the rising edge.
Active low output notifies thermal shutdown has occurred
circuit or other fault that causes the die temperature to become excessively large, the
thermal shutdown will kick in at a die temperature between 115
fault persists, the device will toggle back and forth between shutdown and normal
operation at a frequency in the tens of Hertz. TS is an open collector output capable of
driving two standard TTL loads. The TS pins of several drivers may be wire-ORed
together and input to a latch to indicate an alarm condition.
Quiet positive supply
. The nominal value is 10V
(V
OH
) greater than the nominal value of +7V, V
maximum value of V
OH
. Whenever V
EE
is lowered to provide margin at the output low
level, V
CC
should also be lowered by the same amount. V
ground with a 10,000 pF chip capacitor placed as close to the pins as possible.
Positive supply for the RC7315 output stage
to minimize the supply noise generated when the output switches. V
bypassed to the ground plane with a 10,000 pF chip capacitor placed as close to the pin
as possible and then immediately connected to V
Quiet negative supply
. The nominal value is -5.2V
(V
OL
) less than the nominal value of -2.2V, V
minimum value of V
OL
. Whenever V
CC
is raised to provide margin at the output high
level, V
EE
should also be raised by the same amount. V
ground with a 10,000 pF chip capacitor placed as close to the pins as possible.
,
OH
and V
OL
respectively
. Pins C
VOL
and C
VOH
should be
GND
1
INH+
INH-
23, 24
SRCA
7
SRCM
TS
3
15
. In the event of a short
°
C and 160
°
C. If the
V
CC
2
±
3%. For output high voltage levels
should be raised 3V above the
CC
CC
should be bypassed to
V
CCO
9
. This supply is brought out separately
CCO
should be
CC
.
V
EE
4, 5,
11, 12, 18,
19, 25, 26
±
5%. For output low voltage levels
should be lowered 3V below the
EE
EE
should be bypassed to