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RC7102
PRODUCT SPECIFICATION
8
A
f
ST
Frequency Stabilization
from Power-up
(cold start)
AC Output Impedance
3
ms
Assumes full supply voltage reached within 1ms
from power-up.
Z
0
40
ohm
Average value during switching transition. Used for
determining series termination value.
24MHz Clock Output (Lump Capacitance Test Load = 20pF)
CPU = 66.6MHz
Min.
Typ. Max.
24.004
+167
57/34
0.5
0.5
Units
MHz
ppm
Parameter
f
f
D
m/n
t
R
t
F
Test Condition/Comments
Determined by PLL divider ratio (see n/m below).
(24.004 – 24)/24
(14.31818MHz x 57/34 = 24.004MHz)
Measured from 0.4V to 2.4V.
Measured from 2.4V to 0.4V.
Frequency, Actual
Deviation from 24MHz
PLL Ratio
Output Rise Edge Rate
Output Fall Edge Rate
2
2
V/ns
V/ns
t
D
f
ST
Duty Cycle
Frequency Stabilization
from Power-up
(cold start)
AC Output Impedance
45%
55
3
%
ms
Measured on rising and falling edge at 1.5V.
Assumes full supply voltage reached within 1ms
from power-up.
Z
0
40
ohm
Average value during switching transition. Used for
determining series termination value.
SDRAM Clock Outputs, SDRAM0:13 (Lump Capacitance Test Load =30pF)
Parameter
f
IN
t
R
t
F
t
SR
t
SF
t
EN
t
DIS
t
PR
t
PF
t
D
Z
O
Min.
0
0.5
0.5
Typ.
Max.
150
1.33
1.33
250
250
8.0
8.0
5.0
5.0
55
Units
MHz
nS
nS
pS
pS
nS
nS
nS
nS
%
Test Conditions/Comments
Input Frequency
Output Rise Time
Output Fall Time
Output Skew, Rising Edge
Output Skew, Falling Edge
Output Enable Time
Output Disable Time
Rising Edge Propagation Delay
Falling Edge Propagation Delay
Duty Cycle
AC Output Impedance
Measured from 0.4V to 2.4V
Measured from 2.4V to 0.4V
1.0
1.0
1.0
1.0
45
Measured at 1.5V
15
48MHz Clock Output (Lump Capacitance Test Load = 20pF)
(continued)
CPU = 66.6MHz
Min.
Typ. Max.
Units
Parameter
Test Condition/Comments