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RC7102
PRODUCT SPECIFICATION
12
A
Writing Data Bytes
Each bit in Data Bytes 0-5 control a particular device func-
tion except for the "reserved" bits which must be written as a
logic 0. Bits are written MSB (most significant bit) first,
which is bit 7. Table 5 gives the bit formats for registers
located in Data Bytes 0-5.
Table 6 details additional frequency selections that are avail-
able through the serial data interface.
Table 7 details the select functions for Byte 0, bits 1 and 0.
Table 5. Data Bytes 0-5 Serial Configuration Map
Bit(s)
Data Byte 0
7
Affected Pin
Pin No.
Control Function
Bit Control
Pin Name
0
1
Default
—
CPU and
PCI
—
—
—
—
Spread Amount - Must equal 1
for Down Spread
SEL_2
SEL_1
SEL_0
Hardware/Software Frequency
Select
Spread Type
±
0.25
±
0.5
0
6
5
4
3
—
—
—
—
See Table 6
See Table 6
See Table 6
Hardware
0
0
0
0
Software
2
—
CPU and
PCI
CPU and
PCI
All Clocks
Center
Down
0
1
7, 8, 10, 11,
12, 13, 43, 44
All Clocks
Spread Spectrum Clock
Normal
Spread
0
0
Clock Output Tristate
Active
Tristate
0
Data Byte 1
7
6
5
4
3
2
1
0
Data Byte 2
7
6
5
4
3
2
1
0
—
—
—
—
40
41
43
44
—
—
—
—
(Reserved)
(Reserved)
(Reserved)
Test Mode
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
—
—
—
—
—
—
1
1
1
1
1
1
1
1
see Table 7
Low
Low
Low
Low
SDRAM12
SDRAM13
CPU1
CPU0
Active
Active
Active
Active
—
7
—
13
12
11
10
8
—
(Reserved)
Clock Output Disable
(Reserved)
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
—
Low
—
Low
Low
Low
Low
Low
—
1
1
1
1
1
1
1
1
PCI_F
—
PCI5
PCI4
PCI3
PCI2
PCI1
Active
—
Active
Active
Active
Active
Active