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PRODUCT SPECIFICATION
RC5054A
9
P
required to slew the inductor current from an initial current
value to the transient current level. During this interval the
difference between the inductor current and the transient
current level must be supplied by the output capacitor. Mini-
mizing the response time can minimize the output capaci-
tance required.
The response time to a transient is different for the applica-
tion of load and the removal of load. The following equations
give the approximate response time interval for application
and removal of a transient load:
where: I
TRAN
is the transient load current step, t
RISE
is the
response time to the application of load, and t
FALL
is the
response time to the removal of load. With a +5V input
source, the worst case response time can be either at the
application or removal of load and dependent upon the
DACOUT setting. Be sure to check both of these equations
at the minimum and maximum output levels for the worst
case response time.
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic capaci-
tors for high frequency decoupling and bulk capacitors to
supply the current needed each time Q1 turns on. Place the
small ceramic capacitors physically close to the MOSFETs
and between the drain of Q1 and the source of Q2.
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable oper-
ation, select the bulk capacitor with voltage and current rat-
ings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum input
voltage and a voltage rating of 1.5 times is a conservative
guideline. The RMS current rating requirement for the input
capacitor of a buck regulator is approximately 1/2 the DC
load current.
For a through hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo
MVGX or equivalent) may be needed. For surface mount
designs, solid tantalum capacitors can be used, but caution
must be exercised with regard to the capacitor surge current
rating. These capacitors must be capable of handling the
surge-current at power-up. The TPS series available from
AVX, and the 593D series from Sprague are both surge
current tested.
MOSFET Selection/Considerations
The RC5054A requires 2 N-Channel power MOSFETs.
These should be selected based upon R
DS(ON)
, gate supply
requirements, and thermal management requirements.
In high-current applications, the MOSFET power dissipa-
tion, package selection and heatsink are the dominant design
factors. The power dissipation includes two loss compo-
nents; conduction loss and switching loss. The conduction
losses are the largest component of power dissipation for
both the upper and the lower MOSFETs. These losses are
distributed between the two MOSFETs according to duty
factor (see the equations below). Only the upper MOSFET
has switching losses, since the Schottky rectifier clamps the
switching node before the synchronous rectifier turns on.
These equations assume linear voltage-current transitions
and do not adequately model power loss due the reverse-
recovery of the lower MOSFET’s body diode. The gate-
charge losses are dissipated by the RC5054A and don't heat
the MOSFETs. However, large gate-charge increases the
switching interval,
t
SW
which increases the upper MOSFET switching losses.
Ensure that both MOSFETs are within their maximum junc-
tion temperature at high ambient temperature by calculating
the temperature rise according to package thermal-resistance
specifications. A separate heatsink may be necessary depend-
ing upon MOSFET power, package type, ambient tempera-
ture and air flow.
P
LOWER
Where: D is the duty cycle = V
OUT
/V
IN
,
t
SW
is the switching interval, and
F
S
is the switching frequency
Standard-gate MOSFETs are normally recommended for
use with the RC5054A. However, logic-level gate MOSFETs
can be used under special circumstances. The input voltage,
upper gate drive level, and the MOSFET’s absolute gate-
to-source voltage rating determine whether logic-level
MOSFETs are appropriate.
Figure 7 shows the upper gate drive (BOOT pin) supplied by
a bootstrap circuit from V
CC
. The boot capacitor, C
BOOT
develops a floating supply voltage referenced to the PHASE
pin. This supply is refreshed each cycle to a voltage of V
CC
less the boot diode drop (V
D
) when the lower MOSFET,
Q2 turns on. Logic-level MOSFETs can only be used if the
MOSFET’s absolute gate-to-source voltage rating exceeds
the maximum voltage applied to V
CC
.
t
RISE
L
I
V
OUT
–
V
IN
------------------------------
=
t
FALL
L
-------------------------
I
V
OUT
=
P
UPPER
I
O
2
R
DS ON
)
D
1
V
IN
t
SW
F
S
′
′
′
+
′
′
=
I
O
2
R
DS ON
)
1
D
–
(
)
′
′
=