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PRODUCT SPECIFICATION
RC5051
13
determined by the transient response and the output ripple
voltage, and these are determined by the ESR and not the
capacitance value. That is, in order to achieve the necessary
ESR to meet the transient and ripple requirements, the
capacitance value required is already very large.
The most commonly used choice for output bulk capacitors
is aluminum electrolytics, because of their low cost and low
ESR. The only type of aluminum capacitor used should be
those that have an ESR rated at 100kHz. Consult Application
Bulletin AB-14 for detailed information on output capacitor
selection.
The output capacitance should also include a number of
small value ceramic capacitors placed as close as possible to
the processor; 0.1
m
F and 0.01
m
F are recommended values.
Input Filter
The DC-DC converter design may include an input inductor
between the system +5V supply and the converter input as
shown in Figure 6. This inductor serves to isolate the +5V
supply from the noise in the switching portion of the DC-DC
converter, and to limit the inrush current into the input capac-
itors during power up. A value of 2.5
m
H is recommended.
It is necessary to have some low ESR aluminum electrolytic
capacitors at the input to the converter. These capacitors
deliver current when the high side MOSFET switches on.
Figure 6 shows 3 x 1000
m
F, but the exact number required
will vary with the speed and type of the processor. For the
top speed Klamath and Deschutes, the capacitors should be
rated to take 7A of ripple current. Capacitor ripple current
rating is a function of temperature, and so the manufacturer
should be contacted to find out the ripple current rating at the
expected operational temperature. For details on the design
of an input filter, refer to Applications Bulletin AB-15.
Figure 6. Input Filter
Droop Resistor
Figure 7 shows a converter using a “droop resistor”, R
D
. The
function of the droop resistor is to improve the transient
response of the converter, potentially reducing the number of
output capacitors required. In operation, the droop resistor
causes the output voltage to be slightly lower at heavy load
current than it otherwise would be. When the load transitions
from heavy to light current, the output can swing up farther
without exceeding limits, because it started from a lower
voltage, thus reducing the capacitor requirements.
.
Figure 7. Use of a Droop Resistor
PCB Layout Guidelines
Placement of the MOSFETs relative to the RC5051 is
critical. Place the MOSFETs such that the trace length of
the HIDRV and LODRV pins of the RC5051 to the FET
gates is minimized. A long lead length on these pins will
cause high amounts of ringing due to the inductance of the
trace and the gate capacitance of the FET. This noise
radiates throughout the board, and, because it is switching
at such a high voltage and frequency, it is very difficult to
suppress.
In general, all of the noisy switching lines should be kept
away from the quiet analog section of the RC5051. That
is, traces that connect to pins 9, 12, and 13 (LODRV,
HIDRV and VCCQP) should be kept far away from the
traces that connect to pins 1 through 5, and pin 16.
Place the 0.1
m
F decoupling capacitors as close to the
RC5051 pins as possible. Extra lead length on these
reduces their ability to suppress noise.
Each VCC and GND pin should have its own via to the
appropriate plane. This helps provide isolation between
pins.
Surround the CEXT timing capacitor with a ground trace.
Be sure to place a ground or power plane underneath the
capacitor for further noise isolation, in order to provide
additional shielding to the oscillator (pin 1) from the noise
on the PCB. In addition, place this capacitor as close to
pin 1 as possible.
Place the MOSFETs, inductor, and Schottky as close
together as possible for the same reasons as in the first
bullet above. Place the input bulk capacitors as close to
the drains of the high side MOSFETs as possible. In
addition, placement of a 0.1
m
F decoupling cap right on
the drain of each high side MOSFET helps to suppress
some of the high frequency switching noise on the input
of the DC-DC converter.
Place the output bulk capacitors as close to the CPU as
possible to optimize their ability to supply instantaneous
current to the load in the event of a current transient.
Additional space between the output capacitors and the
CPU will allow the parasitic resistance of the board traces
to degrade the DC-DC converter’s performance under
severe load transient conditions, causing higher voltage
deviation. For more detailed information regarding
capacitor placement, refer to Application Bulletin AB-5.
1000
μ
F, 10V
Electrolytic
0.1
μ
F
65-5051-09
2.5
μ
H
5V
Vin
65-5051-14
L2
Q1
Q2
IFB
VFB
R
SENSE
R
DROOP
C
OUT
VO