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RC5011
PRODUCT SPECIFICATION
4
A
Test Circuit
Figure 1. Standard Test Circuit Schematic
RC5011
VBAT
D1
IN5817
R6
110K
5VIN
EN5V
CX
L1
10
μ
H
R7
13.3K
CX
GND
EN12V
8
M1
Si9410
+12V
7
6
5
VBAT
VOUT
DRV
VFB
1
2
100pF
C1
300
μ
F
EN5V
EN12V
3
4
+5V
Application Information
Step-Up (Boost mode) Converter
A complete schematic of the minimum step-up converter
application is shown in Figure 1. Upon application of power
(V
BAT
) and a logic high signal on the EN5V pin, the fixed
5V precision bandgap reference will become active and
source up to 40mA of load current. If the 5V regulator is not
needed, a logic low on the EN5V pin will disable the 5V reg-
ulator and reduce the supply current, thus minimizing power
consumption. A 1
m
F capacitor connected from the 5V output
to ground is recommended to reduce noise on the 5V output.
A logic high signal placed on the EN12V pin enables the
switch mode regulator. Included in the switch-mode control-
ler is a precision bandgap regulator that generates both a
1.25V reference and a 4V reference internally. The 4V refer-
ence is effectively “filtered ” from the V
BAT
supply to
increase the power supply rejection of the IC, thus making it
less susceptable to changes in the battery voltage and noise.
The 1.25V reference is used for comparison against the
divided down output voltage occuring at the voltage feedback
(VFB) input.
A voltage supply connected to one side of the inductor as
shown will cause the filter capacitor to instantaneously
charge to V
BAT
-V
F
, where V
F
is the forward voltage of the
blocking diode. The voltage on the output capacitor C1 is
also applied to resistor voltage divider R6 and R7, where the
ratio of these resistors determines the final output voltage.
The VFB node is connected to one side (-input) of a voltage
comparator and the other side (+input) is connected to the
1.25V reference. If the voltage across C1 is less than the pro-
grammed value set by the ratio of R6 and R7, the output of
the comparator will be at logic high.
One input of a NAND logic gate is connected to the compar-
ator output, while the other NAND input is connected to the
oscillator output. A logic high will allow the NAND output to
respond to the oscillator input, thus allowing the totem-pole
inverter to pulse the gate of the external N-channel MOSFET.
The totem-pole inverter is referenced to V
BAT
since this
higher voltage will allow a higher gate drive and reduce the
R
DS,ON
value of the MOSFET. When the FET is turned on,
the inductor conducts current to ground through the FET.
When the FET is turned off, diode D1 charges the output
capacitor C1.
The VFB node will continuously monitor the output voltage
and allow the oscillator to drive the MOSFET until the volt-
age at VFB surpasses the internal 1.25V reference voltage. At
this time the output of the comparator switches to a logic low
state, which forces the NAND output high. The totem-pole
inverter will then transition low and turn off the MOSFET.
Because the output voltage is now higher than V
BAT
, the
blocking diode prevents any further current flow into the out-
put capcitor or the load. This condition will remain until the
output voltage drops enough to lower the VFB node below
1.25V, at which time the process starts again. Using this sys-
tem, the feedback network will vary the MOSFET duty cycle
in response to changes in load current or battery voltage.
The inductor value and oscillator frequency must be carefully
tailored to the battery voltage, output current, and ripple
requirements of the application. If either the inductor value or
the oscillator frequency is too high, the inductor current will
never reach a value high enough to meet the load current
drain and the output voltage will collapse. If the inductor
value or the oscillator frequency is too low, the inductor cur-
rent will become excessive, causing higher output voltage
ripple, inductor core saturation, or MOSFET destruction due
to over-stress.