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參數(shù)資料
| 型號： | RC32434-400BCI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | IDT TInterprise Integrated Communications Processor |
| 中文描述： | IDT公司TInterprise集成通信處理器 |
| 文件頁數(shù)： | 9/53頁 |
| 文件大?。?/td> | 444K |
| 代理商： | RC32434-400BCI |
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9 of 53
January 19, 2006
IDT RC32434
Pin Charac teristic s
Note:
Some input pads of the RC32434 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate
levels. This is especially critical for unused control signal inputs (such as WAITACKN) which, if left floating, could adversely affect the
RC32434’s operation. Also, any input pin left floating can cause a slight increase in power consumption.
EJTAG_TMS
I
EJTAG Mode
. The value on this signal controls the test mode select of the
EJTAG Controller. When using the JTAG boundary scan, this pin should be left
disconnected (since there is an internal pull-up) or driven high.
JTAG_TRST_N
I
JTAG Reset
. This active low signal asynchronously resets the boundary scan
logic, JTAG TAP Controller, and the EJTAG Debug TAP Controller. An external
pull-up on the board is recommended to meet the JTAG specification in cases
where the tester can access this signal. However, for systems running in func-
tional mode, one of the following should occur:
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
3) clock JTAG_TCK while holding EJTAG_TMS and/or JTAG_TMS high.
JTAG_TCK
I
JTAG Clock
. This is an input test clock used to clock the shifting of data into or
out of the boundary scan logic, JTAG Controller, or the EJTAG Controller.
JTAG_TCK is independent of the systemand the processor clock with a nom-
nal 50% duty cycle.
JTAG_TDO
O
JTAG Data Output
. This is the serial data shifted out fromthe boundary scan
logic, JTAG Controller, or the EJTAG Controller. When no data is being shifted
out, this signal is tri-stated.
JTAG_TDI
I
JTAG Data Input
. This is the serial data input to the boundary scan logic, JTAG
Controller, or the EJTAG Controller.
System
CLK
I
Master Clock.
This is the master clock input. The processor frequency is a mul-
tiple of this clock frequency. This clock is used as the systemclock for all mem-
ory and peripheral bus operations.
EXTBCV
I
Load External Boot Configuration Vector.
When this pin is asserted (i.e.,
high) the boot configuration vector is loaded froman externally supplied value
during a cold reset.
EXTCLK
O
External Clock.
This clock is used for all memory and peripheral bus opera-
tions.
COLDRSTN
I
Cold Reset.
The assertion of this signal initiates a cold reset. This causes the
processor state to be initialized, boot configuration to be loaded, and the internal
PLL to lock onto the master clock (CLK).
RSTN
I/O
Reset.
The assertion of this bidirectional signal initiates a warmreset. This sig-
nal is asserted by the RC32434 during a warmreset.
S ignal
Type
Name/Desc ription
Table 1 Pin Description (Part 6 of 6)
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