參數(shù)資料
型號(hào)： RC32434-400BC
廠商： Integrated Device Technology, Inc.
英文描述： IDT TInterprise Integrated Communications Processor
中文描述： IDT公司TInterprise集成通信處理器
文件頁(yè)數(shù)： 31/53頁(yè)
文件大?。?/td> 444K
代理商： RC32434-400BC
31 of 53
January 19, 2006
IDT RC32434
Figure 16 SPI AC Timing Waveform —Clock Polarity 0, Clock Phase 0
Figure 17 SPI AC Timing Waveform —Clock Polarity 0, Clock Phase 1
S ignal
S ymbol
Referenc e
E dge
266MHz
300MHz
350MHz
400MHz
Unit
Condi-
tions
T iming
Diagram
Referenc e
Min
Max
Mn
Max
Mn
Max
Mn
Max
SPI
1
1.
In SPI mode, the SCK period and sampling edge are programmable. In PCI mode, the SCK period is fixed and the sampling edge is rising.
SCK
Tper_15a
None
100
166667
100
166667
100
166667
100
166667
ns
SPI
See Figures
16, 17, and 18.
Thigh_15a,
Tlow_15a
40
83353
40
83353
40
83353
40
83353
ns
SPI
SDI
Tsu_15b
SCK rising or
falling
60
—
60
—
60
—
60
—
ns
SPI
See Figures
16, 17, and 18.
Thld_15b
60
—
60
—
60
—
60
—
ns
SPI
SDO
Tdo_15c
SCK rising or
falling
0
60
0
60
0
60
0
60
ns
SPI
SCK, SDI,
SDO
Tpw_15e
None
2(ICLK)
—
2(ICLK)
—
2(ICLK)
—
2(ICLK)
—
ns
Bit I/O
Table 13 SPI AC Timing Characteristics
Tdo_15c
bit 4
Thld_15b
Tsu_15b
bit 3
Tlow_15a
Thigh_15a
Tper_15a
MSB
bit 6
bit 5
bit 3
bit 2
bit 1
LSB
Control bits CPOL = 0, CPHA = 0 in the SPI Control Register, SPC.
MSB
bit 6
bit 4
bit 2
LSB
bit 5
bit 1
SCK
SDI
SDO
Tdo_15c
bit 6
Thld_15b
Tsu_15b
Tlow_15a
Thigh_15a
Tper_15a
MSB
bit 4
bit 5
bit 3
bit 2
bit 1
LSB
Control bits CPOL = 0, CPHA = 1 in the SPI Control Register, SPC.
MSB
bit 6
bit 4
bit 5
bit 3
bit 1
bit 2
LSB
SCK
SDI
SDO
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