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PRODUCT SPECIFICATION
RC5040
9
Figure 4. Typical Switching Waveforms
Main Control Loop
Refer to the Block Diagram on page 1. The control loop of
the regulator contains two main sections; the analog control
block and the digital control block. The analog block con-
sists of signal conditioning amplifiers feeding into a set of
comparators which provide the inputs to the
digital block. The signal conditioning section accepts inputs
from the IFB (current feedback) and VFB (voltage feedback)
pins and sets up two controlling signal paths.
The voltage control path amplifies the VFB signal and
presents the output to one of the summing amplifier inputs.
The current control path takes the difference between the
IFB and VFB pins and presents the resulting signal to
another input of the summing amplifier. These two signals
are then summed together with the slope compensation input
from the oscillator. This output is then presented to a com-
parator, which provides the main PWM control signal to the
digital control block.
The additional comparators in the analog control section set
the thresholds of where the RC5040 enters its pulse skipping
mode during light loads as well as the point at which the
maximum current comparator disables the output drive
signals to the external power MOSFETs.
The digital control block is designed to take the comparator
inputs along with the main clock signal from the oscillator
and provide the appropriate pulses to the HIDRV output
pin that controls the external power MOSFET. The digital
section was designed utilizing high speed Schottky transistor
logic, thus allowing the RC5040 to operate at clock speeds
as high as 1MHz.
High Current Output Drivers
The RC5040 contains two identical high current output
drivers which utilize high speed bipolar transistors arranged
in a push-pull configuration. Each driver is capable of deliv-
ering 1A of current in less than 100ns. Each driver's power
and ground are separated from the overall chip power and
ground for additional switching noise immunity. The HIDRV
driver has a power supply, VCCQP, which is boot-strapped
from a flying capacitor as illustrated in Figure 2. Using this
configuration, C12 is alternately charged from VCC via the
Schottky diode DS2 and then boosted up when the FET is
turned on. This scheme provides a VCCQP voltage equal to
2VCC – VDS(DS2), or approximately 9.5V with VCC =
5V. This voltage is sufficient to provide the 9V gate drive to
the external MOSFET required in order to achieve a low
R
DS(ON)
. Since the low side synchronous FET is referenced to
ground (refer to Figure 4), there is no need to boost the gate
drive voltage and its VCCP power pin can be tied to VCC.
See Typical Operating Characteristics for typical full load
VCCQP waveform.
Internal Voltage Reference
The reference included in the RC5040 is a 1.24V precision
band-gap voltage reference. The internal resistors are pre-
cisely trimmed to provide a near zero temperature coefficient
(TC). Added to the reference input is the resulting output
from an integrated 4-bit DAC. The DAC is provided in
accordance with the Pentium
Pro specification guideline,
which requires the DC-DC converter output to be directly
programmable via a 4-bit voltage identification (VID) code.
This code will scale the reference voltage from 2.0V (no
CPU) to 3.5V in 100mV increments. For guaranteed stable
operation under all loading conditions, a 10K
W
pull-up resis-
tor and 0.1
m
F of decoupling capacitance should be con-
nected to the VREF pin.
Power Good
The RC5040 Power Good function is designed in accordance
with the Pentium
Pro DC-DC converter specification and
provides a constant voltage monitor on the VFB pin. The
circuit compares the VFB signal to the VREF voltage and
outputs an active-low interrupt signal to the CPU should the
power supply voltage exceed
±
7% of its nominal setpoint.
The Power Good flag provides no other control function to
the RC5040.
PWM/PFM
Control
65-5040-12
OSCILLATOR
VO
+5V
VCCQP
HIDRV
LODRV
GNDP
CEXT
CEXT
A
HIDRV
I
LOAD
A
B
B
C
C
D
D
E
E