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PRODUCT SPECIFICATION
RC5037
9
P
Since the value of the sense resistor is often less than 10m
W
,
care should be taken in the layout of the PCB. Trace resis-
tance can contribute significant errors. The traces to the
IFBH and IFBL pins of the RC5037 should be Kelvin con-
nected to the pads of the current-sense resistor. To minimize
the influence of noise, the two traces should be run next to
each other.
Thermal Design Considerations
Good thermal management is critical in the design of high
current regulators. System reliability will be degraded if the
component temperatures become excessive. The following
guide should serve as a reference for proper thermal manage-
ment.
MOSFET Temperature
The maximum power dissipation of the MOSFET can be cal-
culated by using the following formula:
For IRL3103,
Q
JA
is 62
°
C/W. For reliability the junction
temperature of the MOSFET should not exceed 120
°
C.
Assuming that the ambient temperature is 40
°
C, then the
maximum power dissipation without heat sink is calculated
as:
The power that the MOSFET dissipates at 10A load is calcu-
lated as follows:
where V
D
is the forward voltage of the Schottky diode used.
Using the above formula, for V
out
= 3.3V, I
LOAD
= 10A
Since the power at 10A is higher than the thermal guideline,
a heat sink is required.
Schottky Diode
In Figure 10, MOSFET Q1 and flyback diode D1 are used as
complementary switches in order to maintain a constant cur-
rent through the output inductor L2. As a result, D1 will have
to carry the full current of the output load when the power
MOSFET is turned off. The power in the diode is a direct
function of the forward voltage at the rated load current dur-
ing the off time of the FET. The following equation can be
used to estimate the diode power:
where I
D
is the forward current of the diode, V
D
is the for-
ward voltage of the diode, and DutyCycle is defined the
same as above.
For the Motorola MBR1545CT Rectifier in Figure 10,
It is recommended that the diode T0-220 package be
attached to a heatsink.
Board Design Considerations
MOSFET Placement
Placement of the power MOSFET is critical in the design of
the switch-mode regulator. The FET should be placed in
such a way as to minimize the length of the gate drive path
from the RC5037 SDRV pin. This trace should be kept under
0.5" for optimal performance. Excessive lead length on this
trace will cause high frequency noise resulting from the par-
asitic inductance and capacitance of the trace. Since this
voltage can transition nearly 12V in around 100nsec, the
resultant ringing and noise would be very difficult to sup-
press. This trace should be routed on one layer only and kept
well away from the “quiet” analog pins of the device: CEXT,
IFBH, IFBL, and GND. A 4.7
W
resistor in series with the
MOSFET gate can decrease this layout criticality. Refer to
Figure 10.
Inductor and Schottky Diode Placement
The inductor and fly-back Schottky diode need to be placed
close to the source of the power MOSFET for the same rea-
sons stated above. The node connecting the inductor and
Schottky diode will swing between the drain voltage of the
FET and the forward voltage of the Schottky diode. It is rec-
ommended that this node be converted to a plane if possible.
This node will be part of the high current path in the design,
and as such it is best treated as a plane in order to minimize
the parasitic resistance and inductance on that node. Since
most PC board manufacturers utilize 1/2 oz copper on the
5
6
7
8
9
10
13
10.1
8.6
7.5
6.6
5.9
5.4
4.2
12.9
10.9
9.5
8.4
7.5
6.8
5.3
P
D
T
----------------------------------
T
A
–
Q
JA
=
P
D
120
40
–
62
1.29W
=
=
P
MOSFET
V
I
LOAD
2
R
DS ON
I
)
Duty Cycle
(
)
-------------6
t
r
t
f
+
(
)
f
′
′
+
′
′
=
Duty Cycle
V
(
V
D
+
IN
V
D
I
LOAD
R
DS ON
)
′
)
+
V
=
Duty Cycle
0.65
10
+
(
5
0.65
0.023
′
)
–
+
----------------3.3
73.1%
=
=
P
MOSFET
10A
(
)
2
0.025
W
73.1%
5V
10A
′
6
210ns
54ns
+
)
300KHz
′
′
+
′
′
=
P
MOSFET
2.49W
=
P
DIODE
I
D
V
D
1
DutyCycle
–
(
)
′
′
=
P
DIODE
10A
0.65
1
73.1%
–
(
)
′
′
1.75W
=
=