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參數(shù)資料
| 型號： | RBHV57009DG |
| 廠商： | SUPERTEX INC |
| 元件分類： | 顯示驅(qū)動器 |
| 英文描述： | 64-Channel Serial To Parallel Converter With P-Channel Open Drain Controllable Output Current |
| 中文描述： | DC PLASMA DISPLAY DRIVER, CQFP80 |
| 封裝： | CERAMIC, QFP-80 |
| 文件頁數(shù)： | 5/7頁 |
| 文件大?。?/td> | 486K |
| 代理商： | RBHV57009DG |
5
HV57009
HV
OUT
1
HV
OUT
2
HV
OUT
3
HV
OUT
33
HV
OUT
34
HV
OUT
35
Latch
Latch
Latch
Latch
Programmable
Current
V
DD
V
SS
BL
LE
SR2
SR1
CLK
DIR
V
BP
+IN
-IN
HV
OUT
32
HV
OUT
64
D
I/O
2A D
I/O
1A
D
I/O
2B D
I/O
1B
I/O
I/O
Inputs
Outputs
Function
Data In
CLK
LE
BL
DIR
Shift Reg
HV Outputs
Data Out
All O/P High
X
X
L
H
H
H
H
Data Stored in Latches
X
L
H
I/O Relation
H
H
L
H
L
H
H
H
X
L
H
X
D
I/O
1-2A
D
I/O
1-2A
D
I/O
1-2B
D
I/O
1-2B
Figure 4: Function Table
X
X
X
X
H
H
L
L
*
L....L
H....H
*
Q
n
→
Q
n+1
Q
n
→
Q
n+1
Q
n
→
Q
n-1
Q
n
→
Q
n-1
ON
ON
OFF
New ON or OFF
Previous ON or OFF
Previous ON or OFF
New ON or OFF
Notes:
* = dependent on previous stage’s state. See Figure 7 for D
IN
and D
OUT
pin designation for CW and CCW shift.
H = V
DD
(Logic)/V
NN
(HV Outputs)
L = V
SS
Note:
Each SR (shift register) provides 32 outputs. SR1 supplies outputs 1 to 32 and SR2 supplies outputs 33 to 64.
Figure 3: Functional Block Diagram
Inversion of
Stored Data
Data Falls Through
(Latches Tansparent)
*
L
H
*
D
I/O
1-2B
D
I/O
1-2B
D
I/O
1-2A
D
I/O
1-2A
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