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參數(shù)資料
| 型號： | RBHV57009DG |
| 廠商： | SUPERTEX INC |
| 元件分類： | 顯示驅(qū)動器 |
| 英文描述： | 64-Channel Serial To Parallel Converter With P-Channel Open Drain Controllable Output Current |
| 中文描述： | DC PLASMA DISPLAY DRIVER, CQFP80 |
| 封裝： | CERAMIC, QFP-80 |
| 文件頁數(shù)： | 2/7頁 |
| 文件大?。?/td> | 486K |
| 代理商： | RBHV57009DG |
2
Symbol
Parameter
Min
Max
Units
Conditions
I
DD
V
DD
supply current
15
mA
V
DD
= V
DD
, max
f
CLK
= 8MHz
Outputs off,HV
OUT
= -85V
(total of all outputs)
I
NN
High voltage supply current
-10
μ
A
I
DDQ
Quiescent V
DD
supply current
100
μ
A
All inputs = V
DD
, except
+IN = V
SS
= GND
I
O
= -100
μ
A
I
O
= -2mA
I
O
= 100
μ
A
V
IH
= V
DD
V
IL
= 0V
V
REF
= 2V, R
EXT
= 1K,
see Figures 8a and 8b
V
OH
High-level output
Data out
V
DD
-0.5
+1
V
HV
OUT
Data out
V
DD
+0.5
V
V
OL
I
IH
I
IL
I
CS
Low-level output
V
High-level logic input current
1
μ
A
Low-level logic input current
-1
μ
A
HV output source current
-2
mA
-0.1
mA
V
REF
= 0.1V, R
EXT
= 1K,
see Figure 8a and 8b
I
CS
HV output source current for I
REF
= 2.0mA
10
%
V
REF
= 2V, R
EXT
= 1K
Electrical Characteristics
DC Characteristics
(All voltages are referenced to V
SS
, V
SS
= 0, TA = 25
°
C)
Symbol
Parameter
Min
Max
Units
Conditions
f
CLK
t
WL
, t
WH
t
SU
t
H
t
ON
, t
OFF
t
DHL
t
DLH
t
DLE
t
WLE
t
SLE
t
r
, t
f
Clock frequency
Clock width high or low
Data set-up time before clock rises
Data hold time after clock rises
Time for latch enable to HV
OUT
Delay time clock to data high to low
Delay time clock to data low to high
Delay time clock to LE low to high
Width of LE pulse
LE set-up time before clock rises
Maximum allowable clock rise and fall time
(10% and 90% points)
DC
62
10
15
8
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Per register
500
70
70
C
L
= 15pF
C
L
= 15pF
C
L
= 15pF
25
25
0
100
AC Characteristics
(Logic signal inputs and Data inputs have t
r
, t
f
≤
5ns [10% and 90% points] for measurements)
Notes
1: Current going out of the chip is considered negative.
HV57009
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