參數(shù)資料
型號： R5F562N8ADFP#V0
廠商： Renesas Electronics America
文件頁數(shù)： 90/148頁
文件大小： 0K
描述： MCU 32BIT FLASH 512KROM 100LQFP
產(chǎn)品培訓(xùn)模塊： RX Compare Match Timer
RX DMAC
標準包裝： 1
系列： RX600
核心處理器： RX
芯體尺寸： 32-位
速度： 100MHz
連通性： EBI/EMI，I²C，SCI，SPI，USB
外圍設(shè)備： DMA，LVD，POR，PWM，WDT
輸入/輸出數(shù)： 72
程序存儲器容量： 512KB（512K x 8）
程序存儲器類型： 閃存
RAM 容量： 96K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10/12b，D/A 1x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-LQFP
包裝： 托盤
PIC18F6520/8520/6620/8620/6720/8720
DS39609B-page 44
2004 Microchip Technology Inc.
4.3
Fast Register Stack
A “fast interrupt return” option is available for interrupts.
A Fast Register Stack is provided for the Status, WREG
and BSR registers and is only one in depth. The stack
is not readable or writable and is loaded with the
current value of the corresponding register when the
processor vectors for an interrupt. The values in the
registers are then loaded back into the working regis-
ters, if the FAST RETURN instruction is used to return
from the interrupt.
A low or high priority interrupt source will push values
into the stack registers. If both low and high priority
interrupts are enabled, the stack registers cannot be
used reliably for low priority interrupts. If a high priority
interrupt occurs while servicing a low priority interrupt,
the stack register values stored by the low priority
interrupt will be overwritten.
If high priority interrupts are not disabled during low
priority interrupts, users must save the key registers in
software during a low priority interrupt.
If no interrupts are used, the fast register stack can be
used to restore the Status, WREG and BSR registers at
the end of a subroutine call. To use the fast register
stack for a subroutine call, a FAST CALL instruction
must be executed.
Example 4-1 shows a source code example that uses
the fast register stack.
EXAMPLE 4-1:
FAST REGISTER STACK
CODE EXAMPLE
4.4
PCL, PCLATH and PCLATU
The program counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21 bits
wide. The low byte is called the PCL register; this reg-
ister is readable and writable. The high byte is called
the PCH register. This register contains the PC<15:8>
bits and is not directly readable or writable; updates to
the PCH register may be performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC<20:16> bits and is not directly
readable or writable; updates to the PCU register may
be performed through the PCLATU register.
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the LSB of the PCL is fixed to a value of
‘0’. The PC increments by 2 to address sequential
instructions in the program memory.
The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
The contents of PCLATH and PCLATU will be trans-
ferred to the program counter by an operation that
writes PCL. Similarly, the upper two bytes of the
program counter will be transferred to PCLATH and
PCLATU by an operation that reads PCL. This is useful
for computed offsets to the PC (see Section 4.8.1
4.5
Clocking Scheme/Instruction
Cycle
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the
program counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruc-
tion is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
are shown in Figure 4-4.
FIGURE 4-4:
CLOCK/INSTRUCTION CYCLE
CALL SUB1, FAST
;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
SUB1
RETURN FAST
;RESTORE VALUES SAVED
;IN FAST REGISTER STACK
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Q3
Q4
PC
OSC2/CLKO
(RC mode)
PC
PC+2
PC+4
Fetch INST (PC)
Execute INST (PC-2)
Fetch INST (PC+2)
Execute INST (PC)
Fetch INST (PC+4)
Execute INST (PC+2)
Internal
Phase
Clock
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R5F56217BDBG#U0 MCU 32BIT FLASH 384KROM 176LFBGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
R5F562N8ADLE 制造商:Renesas Electronics Corporation 功能描述:MCU 32BIT RX62N 145LGA 制造商:Renesas Electronics Corporation 功能描述:MCU, 32BIT, RX62N, 145LGA 制造商:Renesas Electronics Corporation 功能描述:MCU, 32BIT, RX62N, 145LGA, Controller Family/Series:RX600, Core Size:32bit, No. of I/O's:103, Supply Voltage Min:2.7V, Supply Voltage Max:3.6V, Digital IC Case Style:LGA, No. of Pins:145, Program Memory Size:512KB, RAM Memory , RoHS Compliant: Yes
R5F562N8ADLE#U0 功能描述:MCU 32BIT FLASH 512KROM 145TFLGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:RX600 標準包裝:1 系列:87C 核心處理器:MCS 51 芯體尺寸:8-位 速度:16MHz 連通性:SIO 外圍設(shè)備:- 輸入/輸出數(shù):32 程序存儲器容量:8KB（8K x 8） 程序存儲器類型:OTP EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4 V ~ 6 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:外部 工作溫度:0°C ~ 70°C 封裝/外殼:44-DIP 包裝:管件 其它名稱:864285
R5F562N8BDBG 制造商:Renesas Electronics Corporation 功能描述:MCU 32BIT RX62N 176BGA 制造商:Renesas Electronics Corporation 功能描述:MCU, 32BIT, RX62N, 176BGA 制造商:Renesas Electronics Corporation 功能描述:MCU, 32BIT, RX62N, 176BGA, Controller Family/Series:RX600, Core Size:32bit, No. of I/O's:126, Supply Voltage Min:2.7V, Supply Voltage Max:3.6V, Digital IC Case Style:LFBGA, No. of Pins:176, Program Memory Size:512KB, RAM Memory , RoHS Compliant: Yes
R5F562N8BDBG#U0 功能描述:MCU 32BIT FLASH 512K ROM 176BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:RX600 標準包裝:1 系列:87C 核心處理器:MCS 51 芯體尺寸:8-位 速度:16MHz 連通性:SIO 外圍設(shè)備:- 輸入/輸出數(shù):32 程序存儲器容量:8KB（8K x 8） 程序存儲器類型:OTP EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4 V ~ 6 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:外部 工作溫度:0°C ~ 70°C 封裝/外殼:44-DIP 包裝:管件 其它名稱:864285
R5F562N8BDFB 制造商:Renesas Electronics Corporation 功能描述:MCU 32BIT RX62N 144QFP
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