參數(shù)資料
型號(hào)： R2043T-E2
廠商： RICOH COMPANY LTD
元件分類： XO, clock
英文描述： 4-wire Serial Interface
中文描述： REAL TIME CLOCK, PDSO10
封裝： 4 X 2.9 MM, 1 MM HEIGHT, TSSOP-10
文件頁(yè)數(shù)： 21/48頁(yè)
文件大?。?/td> 458K
代理商： R2043T-E2
R2043K/T
Q
Interfacing with the CPU
O
DATA TRANSFER FORMATS
(1) Timing Between CE Pin Transition and Data Input / Output
The R2043K/T adopts a 4-wire serial interface by which they use the CE (Chip Enable), SCLK (Serial Clock), SI
(Serial Input), and SO (Serial Output) pins to receive and send data to and from the CPU. The 4-wire serial
interface provides two types of input/output timings with which the SO pin output and the SI pin input are
synchronized with the rising or falling edges of the SCLK pin input, respectively, and vice versa. The R2043K/T
is configured to select either one of two different input/output timings depending on the level of the SCLK pin in
the low to high transition of the CE pin. Namely, when the SCLK pin is held low in the low to high transition of
the CE pin, the models will select the timing with which the SO pin output is synchronized with the rising edge of
the SCLK pin input, and the SI pin input is synchronized with the falling edge of the SCLK pin input, as illustrated
in the timing chart below.
CE
t
CES
12345
Rev.2.05 - 21 -
SCLK
SO
t
DS
SI
t
DH
t
RD
Conversely, when the SCLK pin is held high in the low to high transition of the CE pin, the models will select the
timing with which the SO pin output is synchronized with the falling edge of the SCLK pin input, and the SI pin
input is synchronized with the rising edge of the SCLK pin input, as illustrated in the timing chart below.
CE
t
CES
SCLK
SO
t
DS
SI
t
DH
t
RD
(2) Data Transfer Formats
Data transfer is commenced in the low to high transition of the CE pin input and completed in its high to low
transition. Data transfer is conducted serially in multiple units of 1 byte (8 bits). The former 4 bits are used to
specify in the Address Pointer a head address with which data transfer is to be commenced from the host. The
latter 4 bits are used to select either reading data transfer or writing data transfer, and to set the Transfer Format
Register to specify an appropriate data transfer format. All data transfer formats are designed to transfer the
most significant bit (MSB) first.
CE
6
7
5
2
3
1
4
A2
SCLK
SO
A1
A0
C3
C2
C1
C0
D7
D6
D3
D2
D1
D0
A3
8
2
3
1
D7
D6
D3
D2
D1
D0
Reading data transfer
Setting
the Address Pointer
Writing data transfer
Setting the Transfer
Format Register
SI
Two types of data transfer formats are available for reading data transfer and writing data transfer each.
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