參數資料
型號: R2043K-E2
廠商: RICOH COMPANY LTD
元件分類: XO, clock
英文描述: 4-wire Serial Interface
中文描述: REAL TIME CLOCK, QCC12
封裝: 2 X 2 MM, 1 MM HEIGHT, FFP-12
文件頁數: 39/48頁
文件大?。?/td> 458K
代理商: R2043K-E2
R2043K/T
12345
Rev.2.05 - 39 -
In the pulse mode, the increment of the second counter is delayed by approximately 92
μ
s from the
falling edge of clock pulses. Consequently, time readings immediately after the falling edge of clock
pulses may appear to lag behind the time counts of the real-time clocks by approximately 1 second.
Rewriting the second counter will reset the other time counters of less than 1 second, driving the
/INTR pin low.
*2) Level Mode:
Periodic interrupt signals are output with selectable interrupt cycle settings of 1 second, 1 minute, 1
hour, and 1 month. The increment of the second counter is synchronized with the falling edge of
periodic interrupt signals. For example, periodic interrupt signals with an interrupt cycle setting of 1
second are output in synchronization with the increment of the second counter as illustrated in the
timing chart below.
CTFG Bit
Setting CTFG bit to 0
/INTR Pin
(Increment of
second counter)
(Increment of
second counter)
(Increment of
second counter)
Setting CTFG bit to 0
*1), *2) When the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20sec. as
follows:
Pulse Mode: The “L” period of output pulses will increment or decrement by a maximum of
±
3.784ms. For
example, 1-Hz clock pulses will have a duty cycle of 50
±
0.3784%.
Level Mode: A periodic interrupt cycle of 1 second will increment or decrement by a maximum of
±
3.784 ms.
32-kHz CLOCK OUTPUT
For the R2043K/T, 32.768-kHz clock pulses are output from the 32KOUT pin when either the /CLEN1 bit in
the Control Register 2 or the /CLEN2 bit in the Control Register 1 is set to 0. When both the /CLEN1 and
/CLEN2 bits are set to 0, the 32KOUT pin output is driven high (off).
/CLEN1
(D3 at Address Fh)
(D4 at Address Eh)
(N-channel Open Drain)
1
1
OFF(H)
0(Default)
*
*
0(Default)
The 32KOUT pin output is synchronized with the /CLEN1 and /CLEN2 bit settings as illustrated in the timing
chart below.
O
/CLEN2
32KOUT PIN
Clock pulses
32KOUT PIN
Max.62.0
μ
s
/CLEN1or2
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