參數(shù)資料
型號(hào)： R2033T-E2
廠商： RICOH COMPANY LTD
元件分類： XO, clock
英文描述： 3 wire interface Real-Time Clock ICs
中文描述： 0 TIMER(S), REAL TIME CLOCK, PDSO10
封裝： 4 X 2.90 MM, 1 MM HEIGHT, TSSOP-10
文件頁(yè)數(shù)： 41/50頁(yè)
文件大?。?/td> 542K
代理商： R2033T-E2
R2033K/T
41
INTR Pin
(Increment of
second counter)
CTFG Bit
Setting CTFG bit to 0
Setting CTFG bit to 0
(Increment of
second counter)
(Increment of
second counter)
*1), *2) When the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20sec. as
follows:
Pulse Mode: The “L” period of output pulses will increment or decrement by a maximum of
±
3.784ms. For
example, 1-Hz clock pulses will have a duty cycle of 50
±
0.3784%.
Level Mode: A periodic interrupt cycle of 1 second will increment or decrement by a maximum of
±
3.784ms.
32-kHz CLOCK OUTPUT
For the R2033K/T, 32.768-kHz clock pulses are output from the 32KOUT pin when either the CLEN1 bit in the
Control Register 2 or the CLEN2 bit in the Control Register 1 is set to 0 when the CLKC pin is set to high. If
the condition is not satisfied, the output is set to low.
CLEN1
(D3 at Address Fh)
(D4 at Address Eh)
1
1
*
*
0(Default)
*
*
0(Default)
The 32KOUT pin output is synchronized with the CLEN1 and CLEN2 bit and CLKC pin settings as
illustrated in the timing chart below.
CLEN2
CLKC pin input
32KOUT PIN
(CMOS push-pull output)
“L”
*
0
1
1
Clock pulses
32KOUT PIN
Max.62.0
μ
s
CLKC pin or CLEN1 or
CLEN2 bit setting
相關(guān)PDF資料
PDF描述
R2033K 3 wire interface Real-Time Clock ICs
R2033K-E2 3 wire interface Real-Time Clock ICs
R2033T 3 wire interface Real-Time Clock ICs
R2043T 4-wire Serial Interface
R2043T-E2 4-wire Serial Interface
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