參數(shù)資料
型號(hào)： R2033T-E2
廠商： RICOH COMPANY LTD
元件分類(lèi)： XO, clock
英文描述： 3 wire interface Real-Time Clock ICs
中文描述： 0 TIMER(S), REAL TIME CLOCK, PDSO10
封裝： 4 X 2.90 MM, 1 MM HEIGHT, TSSOP-10
文件頁(yè)數(shù)： 15/50頁(yè)
文件大小： 542K
代理商： R2033T-E2
R2033K/T
15
Control Register 2 (Address Fh)
D7
D6
VDSL
VDET
VDSL
VDET
0
0
*) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD
power-on from 0 volts.
(1) VDSL
VDD Supply Voltage Monitoring Threshold Selection Bit
VDSL
0
Selecting the VDD supply voltage monitoring threshold setting of 2.1v.
1
Selecting the VDD supply voltage monitoring threshold setting of
1.35v.
The VDSL bit is intended to select the VDD supply voltage monitoring threshold settings.
(2) VDET
Supply Voltage Monitoring Result Indication Bit
VDET
0
Indicating supply voltage above the supply voltage monitoring
threshold settings.
1
Indicating supply voltage below the supply voltage monitoring
threshold settings.
Once the VDET bit is set to 1, the supply voltage monitoring circuit will be disabled while the VDET bit will
hold the setting of 1. The VDET bit accepts only the writing of 0, which restarts the supply voltage
monitoring circuit. Conversely, setting the VDET bit to 1 causes no event.
(3)
XST
Oscillation Halt Sensing Monitor Bit
XST
0
Sensing a halt of oscillation
1
Sensing a normal condition of oscillation
The
XST
accepts the reading and writing of 0 and 1. The
XST
bit will be set to 0 when the oscillation
halt sensing. The
XST
bit will hold 0 even after the restart of oscillation.
(4) PON
Power-on-reset Flag Bit
PON
0
Normal condition
1
Detecting VDD power-on -reset
The PON bit is for sensing power-on reset condition.
* The PON bit will be set to 1 when VDD power-on from 0 volts. The PON bit will hold the setting of 1 even
after power-on.
* When the PON bit is set to 1, all bits will be reset to 0, in the Oscillation Adjustment Register, Control
Register 1, and Control Register 2, except
XST
and PON. As a result, INTR pin stops outputting.
* The PON bit accepts only the writing of 0. Conversely, setting the PON bit to 1 causes no event.
D5
XST
XST
Indefinite
D4
PON
PON
1
D3
D2
CTFG
CTFG
0
D1
D0
DAFG
DAFG
0
CLEN1
CLEN1
0
WAFG
WAFG
0
(For Writing)
(For Reading)
Default Settings *)
Description
(Default)
Description
(Default)
Description
Description
(Default)
相關(guān)PDF資料
PDF描述
R2033K 3 wire interface Real-Time Clock ICs
R2033K-E2 3 wire interface Real-Time Clock ICs
R2033T 3 wire interface Real-Time Clock ICs
R2043T 4-wire Serial Interface
R2043T-E2 4-wire Serial Interface
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