參數(shù)資料
型號(hào)： R2025D
廠商： RICOH COMPANY LTD
元件分類： XO, clock
英文描述： High precision I2C-Bus Real-Time Clock Module
中文描述： REAL TIME CLOCK, DSO20
封裝： 6.10 X 5 MM, 1.30 MM HEIGHT, SON-22/20
文件頁(yè)數(shù)： 13/47頁(yè)
文件大?。?/td> 524K
代理商： R2025D
R2025S/D
13
*1), *2) When the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20sec. or
60sec. as follows:
Pulse Mode: The “L” period of output pulses will increment or decrement by a maximum of
±
3.784 ms. For
example, 1-Hz clock pulses will have a duty cycle of 50
±
0.3784%.
Level Mode: A periodic interrupt cycle of 1 second will increment or decrement by a maximum of
±
3.784 ms.
Control Register 2 (Address Fh)
D7
D6
D5
D4
D3
VDSL
VDET
/XST
PON
/CLE
N1
VDSL
VDET
/XST
PON
/CLE
N1
0
0
Indefinit
e
*) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD
power-on from 0 volts.
(1) VDSL
VDD Supply Voltage Monitoring Threshold Selection Bit
VDSL
0
Selecting the VDD supply voltage monitoring threshold setting of
2.1v.
1
Selecting the VDD supply voltage monitoring threshold setting of
1.3v.
The VDSL bit is intended to select the VDD supply voltage monitoring threshold settings.
(2) VDET
Supply Voltage Monitoring Result Indication Bit
VDET
0
Indicating supply voltage above the supply voltage monitoring
threshold settings.
1
Indicating supply voltage below the supply voltage monitoring
threshold settings.
Once the VDET bit is set to 1, the supply voltage monitoring circuit will be disabled while the VDET bit will
hold the setting of 1. The VDET bit accepts only the writing of 0, which restarts the supply voltage
monitoring circuit. Conversely, setting the VDET bit to 1 causes no event.
(3) /XST
Oscillation Halt Sensing Monitor Bit
/XST
0
Sensing a halt of oscillation
1
Sensing a normal condition of oscillation
The /XST accepts the reading and writing of 0 and 1. The /XST bit will be set to 0 when the oscillation halt
sensing. The /XST bit will hold 0 even after the restart of oscillation.
(4) PON
Power-on-reset Flag Bit
D2
D1
D0
CTFG
WAF
G
WAF
G
0
DAFG
(For Writing)
CTFG
DAFG
(For Reading)
1
0
0
0
Default Settings *)
Description
(Default)
Description
(Default)
Description
PON
Description
0
1
Normal condition
Detecting VDD power-on -reset
(Default)
The PON bit is for sensing power-on reset condition.
* The PON bit will be set to 1 when VDD power-on from 0 volts. The PON bit will hold the setting of 1 even
after power-on.
* When the PON bit is set to 1, all bits will be reset to 0, in the Oscillation Adjustment Register, Control
Register 1, and Control Register 2, except /XST and PON. As a result, /INTRA and /INTRB pins stop
outputting.
* The PON bit accepts only the writing of 0. Conversely, setting the PON bit to 1 causes no event.
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