
R2023K/T
Interfacing with the CPU
The R2023K/T employs the I
2
C-Bus system to be connected to the CPU via 2-wires. Connection and system of
I
2
C-Bus are described in the following sections.
Connection of I
2
C-Bus
2-wires, SCL and SDA pins that are connected to I
2
C-Bus are used for transmit clock pulses and data respectively.
All ICs that are connected to these lines are designed that will not be clamped when a voltage beyond supply
voltage is applied to input or output pins. Open drain pins are used for output. This construction allows
communication of signals between ICs with different supply voltages by adding a pull-up resistor to each signal line
as shown in the figure below. Each IC is designed not to affect SCL and SDA signal lines when power to each of
these is turned off separately.
VDD1
VDD2
VDD3
VDD4
21
Micro-
Controller
R2023K/T
Other
Peripheral
Device
SCL
SDA
* For data interface, the following
conditions must be met:
VCC4
≥
VCC1
VCC4
≥
VCC2
VCC4
≥
VCC3
* When the master is one, the
micro-controller is ready for driving
SCL to “H” and Rp of SCL may not be
required.
Rp
Rp
Cautions on determining Rp resistance,
(1) Dropping voltage at Rp due to sum of input current or output current at off conditions on each IC pin connected
to the I
2
C-Bus shall be adequately small.
(2) Rising time of each signal be kept short even when all capacity of the bus is driven.
(3) Current consumed in I
2
C-Bus is small compared to the consumption current permitted for the entire system.
When all ICs connected to I
2
C-Bus are CMOS type, condition (1) may usually be ignored since input current and
off-state output current is extremely small for the many CMOS type ICs. Thus the maximum resistance of Rp may
be determined based on (2), while the minimum on (3) in most cases.
In actual cases a resistor may be place between the bus and input/output pins of each IC to improve noise margins
in which case the Rp minimum value may be determined by the resistance.
Consumption current in the bus to review (3) above may be expressed by the formula below:
Bus consumption current
≈
(Sum of input current and off state output current of all devices in standby mode )
×
Bus standby duration
Bus stand-by duration + the Bus operation duration
+ Supply voltage
×
Bus operation duration
×
2
Rp resistance
×
2
×
(Bus stand-by duration + bus operation duration)
+ Supply voltage
×
Bus capacity
×
Charging/Discharging times per unit time
Operation of “
×
2” in the second member denominator in the above formula is derived from assumption that “L”
duration of SDA and SCL pins are the half of bus operation duration. “
×
2” in the numerator of the same member