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參數(shù)資料
| 型號(hào)： | QLX4300SIQSR |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 4/21頁(yè) |
| 文件大小： | 0K |
| 描述： | IC EQUALIZER REC 3.125GBPS 46QFN |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 系列： | QLx™ |
| 應(yīng)用： | 數(shù)據(jù)傳輸 |
| 接口： | SMBus（2 線/I²C） |
| 電源電壓： | 1.1 V ~ 1.3 V |
| 封裝/外殼： | 46-WFQFN 裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 46-TQFN |
| 包裝： | 帶卷 (TR) |
| 安裝類(lèi)型： | 表面貼裝 |
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12
FN6982.1
November 19, 2009
Channel Power-Down
In addition to controlling the input impedance, the IS[k]
pin powers down the equalizer channel when pulled low.
This feature allows a system controller individually to
power down unused channels and to minimize power
consumption. Example: the signal to power down a
channel could come from an Intelligent Platform
Management controller in ATCA applications for
E-Keying. The current draw for a channel is reduced from
50mA to 3.8mA when powered down.
Applications Information
Several aspects of the QLx4300-S45 are capable of being
dynamically managed by a system controller to provide
maximum flexibility and optimum performance. These
functions are controlled by interfacing to the highlighted
pins in Figure 21. The specific procedures for controlling
these aspects of the QLx4300-S45 are the focus of this
section.
FIGURE 21. PIN DIAGRAM HIGHLIGHTING PINS USED
FOR DYNAMIC CONTROL OF THE
QLx4300-S45
DT
IN1[P]
IN1[N]
VDD
IN2[P]
IN2[N]
VDD
CL
K
ENB
CP1
[A]
CP1
[B]
CP1
[C]
CP2
[B]
CP2
[A]
1
2
3
4
5
6
7
46 45 44
43 42 41 40
8
9
10
11
12
13
14
15
39
16 17 18
19 20
21 22 23
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
IN3[P]
IN3[N]
VDD
IN4[P]
IN43[N]
IS1
IS2
GND
BGREF
OUT1[P]
OUT1[N]
VDD
OUT2[P]
OUT2[N]
VDD
OUT3[P]
OUT3[N]
VDD
OUT4[P]
OUT4[N]
IS3
IS4
MODE
CP
2
[C]
EXPOSED PAD
CP3
[C]
CP4
[B]
DO
CP3
[A]
DI
CP3
[B]
CP4
[A]
CP4
[C]
(GND)
TABLE 1. DESCRIPTIONS OF PINS THAT CAN BE USED TO SET EQUALIZATION BOOST LEVEL
PIN NAME
PIN
NUMBER
DESCRIPTION
DI
16
Serial data input, CMOS logic. Input for serial data stream to program internal registers controlling
the boost for all four equalizers. Synchronized with clock (CLK) on pin 46. Overrides the boost
setting established on CP control pins. Internally pulled down.
DO
17
Serial data output, CMOS logic. Output of the internal registers controlling the boost for all four
equalizers. Synchronized with clock on pin 46. Equivalent to serial data input on DI but delayed by
21 clock cycles.
CP3[A,B,C]
18, 19, 20
Control pins for setting equalizer 3. CMOS logic inputs. Pins are read as a 3-digit number to set the
boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ resistor.
CP4[A,B,C]
21, 22, 23
Control pins for setting equalizer 4. CMOS logic inputs. Pins are read as a 3-digit number to set the
boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ resistor.
MODE
24
Boost-level control mode input, CMOS logic. Allows serial programming of internal registers
through pins DI, ENB, and Clk when set “HIGH”. Resets all internal registers to zero and uses boost
levels set by CP pins when set LOW. If serial programming is not used, this pin should be grounded.
CP2[C,B,A]
39, 40, 41
Control pins for setting equalizer 2. CMOS logic inputs. Pins are read as a 3-digit number to set the
boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ resistor.
CP1[C,B,A]
42, 43, 44
Control pins for setting equalizer 1. CMOS logic inputs. Pins are read as a 3-digit number to set the
boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ resistor.
ENB
45
Serial data enable (active low), CMOS logic. Internal registers can be programmed with DI and CLK
pins only when the ENB pin is ‘LOW’. Internally pulled down.
CLK
46
Serial data clock, CMOS logic. Synchronous clock for serial data on DI and DO pins. Data on DI is
latched on the rising clock edge. Clock speed is recommended to be between 10MHz and 20MHz.
Internally pulled down.
QLx4300-S45
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| QLX4300SIQT7 | 功能描述:接口 - 專(zhuān)用 4 GBS QD CH LANE EXTENDER RoHS:否 制造商:Texas Instruments 產(chǎn)品類(lèi)型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| QLX4600LIQSR | 功能描述:接口 - 專(zhuān)用 6 GBS QD CH LANE EXTENDER RoHS:否 制造商:Texas Instruments 產(chǎn)品類(lèi)型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| QLX4600LIQT7 | 功能描述:接口 - 專(zhuān)用 6 GBS QD CH LANE EXTENDER RoHS:否 制造商:Texas Instruments 產(chǎn)品類(lèi)型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| QLX4600MIBQ15 | 制造商:Intersil Corporation 功能描述:IC LINEAR |
| QLX4600-S30 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Quad Lane Extender |
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