參數(shù)資料
型號(hào)： QL82SD-PB516
廠商： Electronic Theatre Controls, Inc.
英文描述： 10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps
中文描述： 10高速總線LVDS串行鏈路的帶寬高達(dá)5Gbps的
文件頁數(shù)： 32/60頁
文件大?。?/td> 3838K
代理商： QL82SD-PB516
www.quicklogic.com
2002 QuickLogic Corporation
QL82SD Device Data Sheet Rev C
Preliminary
32
LVDS SERDES Channel Clock Configuration
There are two SERDES channel clocks within the core.
Figure 44
shows a representation of
the channel clock. Each channel clock is identical.
Figure 44: SERDES CLK A
Each of the two SERDES channel clocks can be configured independently. They can be
configured to act as the transmit or receive clock for up to 8 SERDES data channels (for serial
links where the clock is provided as a separate LVDS wire pair). Alternatively, the channel
clock can be configured as a simple bi-directional IO pin, where the internal signals are
CMOS, but the external pin is LVDS. In such a case, the I/O will act simply as a level
converter.
Since the channel clock may act as a transmit or receive clock (or as an input or output signal
in data mode), the direction of the channel clock must be selected with the ClkX_oe pin. If
this pin is high, then the channel clock is transmitting a clock (or acting as an output signal
in data mode). If this pin is low, then the channel clock is receiving a clock (or acting as an
input signal in data mode).
When the channel clocks are used to act as the transmit or receive clock for one or more
data channels, then four modes are available, using the CLKx_MODE[1:0] input.
Table 30
shows these modes.
When a channel clock is configured with ClkX_MODE[1:0] equal to 01, 10, or 11, then any
of the data channels can be configured to use that channel clock as its clock, by setting the
data channel's ChX_MODE inputs to point to the correct channel clock. See the
Section ,
“
LVDS SERDES Data Channel Configuration,
”
on page 31
for more information.
When the channel clock is configured with ClkX_MODE[1:0] equal to 00, the channel clock
becomes a simple LVDS-to-CMOS level converter.
When ClkX_oe is high, the channel clock will be configured as an output, in which the data
supplied on the ClkX_txclk pin is converted to LVDS and comes out on the pad_ClkX_p and
pad_ClkX_n external LDVS signals asynchronously.
When ClkX_oe is low, the channel clock is configured as an LVDS input, in which the LVDS
signal on pad_ClkX_p and pad_ClkX_n is converted to CMOS levels and enters the device
on the ClkX_rxclk pin.
Table 30: ClkX_mode[1:0]
ClkX_mode[1:0]
Mode
00
1:1 mode (no PLL)
01
4:1 mode
10
7:1 mode
11
8:1 mode
ClkA_oe
ClkA_en
ClkA_rxclk
ClkA_pre_emp
ClkA_mode[1:0]
ClkA_txclk
pad_ClkA_p
pad_ClkA_n
SERDES
CLKA
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