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參數(shù)資料
| 型號： | QL80FC-APB456C |
| 元件分類： | 通信、網(wǎng)絡(luò)模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁數(shù)： | 8/21頁 |
| 文件大?。?/td> | 757K |
| 代理商： | QL80FC-APB456C |
8
Preliminary
8
QL80FC - QuickFC
TM
Dedicated I/O Pins
Customizable Interface Signals
S
IGNAL
D
EFINITIONS
Async_rst
TxOut[19:0]
TxClk125_in
RxIn[19:0]
RxClk125_in
RxComDet
ResIn[2:0]
input
output
input
input
input
input
input
active high, asynchronous reset
data transmitted to SERDES (only lines [9:0] are used in 10 bit mode)
transmit clock up to 125 MHz
data received from SERDES
receive clock up to 125 MHz
Fibre Channel comma character detected
reserved for QuickLogic use, hold low or high
TenbMode
Clk_rst
TxRst
TxData[31:0]
TxRData[39:32]
input
Input
output
input
input
enables 10 bit interface to SERDES when asserted
Stops TxClk63 and RxClk63 when high. Tie Low.
active high reset signal for transmit path, synchronous with TxClk63
32 bit Fibre Channel word to be encoded for transmit path
only used when TxRawEn is asserted. Combines with TxData to
construct 40 bit raw data for transmit path
enables CRC error value generation when asserted
enables Intra-Frame IDLE support for transmit path when asserted
select between raw and encoded data modes for transmit data path
indicates that the most significant byte of data word is a K character
full speed transmit clock up to 125 MHz (use the rising edge)
half speed transmit clock up to 63 MHz (use the rising edge)
32 bit Fibre Channel word decoded by the ENDEC receive path.
only used when RxRawEn is asserted. Combines with RxData to
construct 40 bit raw data through the ENDEC receive path
select between raw and encoded data modes for receive data path
asserted when most significant byte of data word is a K character
bus indicating when an ordered set is detected. One signal line is asserted
corresponding to the type of ordered set detected:
[0] – SOF
[5] – NOS
[1] – EOF
[6] – LR
[2] – IDLE
[7] – LRR
[3] – R_RDY
[8] – ARB
[4] – OLS
[9] – OPN
asserted when available data is a CRC word
asserted when CRC remainder is zero
enables CRC error checking for the receive data path when asserted
enables Intra-Frame IDLE support for receive path when asserted
asserted when bit synchronization with the SERDES has been lost
index indicating state of Loss of Sync state machine
asserted when available data has an invalid encoding error
full speed receive clock up to 125 MHz (use the rising edge)
half speed receive clock up to 63 MHz (use the rising edge)
active high reset signal for receive data path, synchronous with RxClk63
reserved for QuickLogic use, do not connect to these outputs
TxCrcEn
TxIFIdleEn
TxRawEn
TxKChar
TxClk125
TxClk63
RxData[31:0]
RxRData[39:32]
input
Input
input
input
output
output
output
output
RxRawEn
RxKChar
RxSgpBus[14:0]
input
output
output
[10] – CLS
[11] – MRK
[12] – LIP
[13] – LPE
[14] – LPB
RxCrcRdy
RxCrcOK
RxCrcEn
RxIFIdleEn
RxLOSync
RxLOSIdx[3:0]
RxInvChar
RxClk125
RxClk63
RxRst
ResOut[2:0]
output
output
input
input
output
output
output
output
output
output
output
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| QL80FC-APB456I | Telecomm/Datacomm |
| QL80FC-APQ208C | Telecomm/Datacomm |
| QL80FC-APQ208I | Telecomm/Datacomm |
| QL80FC | Programmable Fibre Channel ENDEC(可編程光纖信道編解碼器) |
| QL82SD | 10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| QL80FC-APB456I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| QL80FC-APQ208C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| QL80FC-APQ208I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| QL8150 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM |
| QL8250 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM |
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