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參數(shù)資料
| 型號： | QL7180-7PT280I |
| 英文描述： | USER PROGRAMMABLE SPECIAL FUNCTION ASIC|CMOS|BGA|280PIN |
| 中文描述： | 用戶可編程特殊功能的ASIC |的CMOS | BGA封裝| 280PIN |
| 文件頁數(shù)： | 6/26頁 |
| 文件大小： | 315K |
| 代理商： | QL7180-7PT280I |
6
www.quicklogic.com
2001 QuickLogic Corporation
QL7180 DSP Data Sheet
Figure 9: RAM Cell Synchronous Write Timing
Table 5: RAM Cell Synchronous & Asynchronous Read Timing
Symbol
Parameter
Propagation
delay (ns)
RAM Cell Synchronous Read Timing
1
TSRA
RA Setup Time to RCLK: the amount of time the READ ADDRESS must
be stable before the active edge of the READ CLOCK
0.686
THRA
RA Hold Time to RCLK: the amount of time the READ ADDRESS must
be stable after the active edge of the READ CLOCK
0
TSRE
RE Setup Time to RCLK: the amount of time the READ ENABLE must
be stable before the active edge of the READ CLOCK
0.243
THRE
RE Hold Time to RCLK: the amount of time the READ ENABLE must be
stable after the active edge of the READ CLOCK
0
TRCRD
RCLK to RD [5]: the amount of time between the active READ CLOCK
edge and the time when the data is available at RD
4.38
RAM Cell Synchronous Read Timing
RPDRD
RA to RD [5]: amount of time between when the READ ADDRESS is
input and when the DATA is output
2.06
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