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參數(shù)資料
| 型號(hào)： | PXA255 |
| 廠商： | Intel Corp. |
| 英文描述： | PXA255 Processor |
| 中文描述： | PXA255處理器 |
| 文件頁數(shù)： | 37/40頁 |
| 文件大?。?/td> | 1191K |
| 代理商： | PXA255 |
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Electrical Specifications
Intel PXA255 Processor
Electrical, Mechanical, and Thermal Specification
37
4.9
Peripheral Module AC Specifications
This section describes the AC specifications for the LCD and SSP peripheral units.
4.9.1
LCD Module AC Timing
Figure 7
describes the LCD timing parameters. The LCD pin timing specifications are referenced
to the pixel clock (L_PCLK). Values for the parameters are given in
Table 23
.
4.9.2
SSP Module AC Timing
Figure 8, “SSP AC Timing Definitions” on page 38
describes the SSP timing parameters. The SSP
pin timing specifications are referenced to SCLK_C. Values for the parameters are given in
Table 24, “SSP AC Timing Specifications” on page 38
.
Figure 7. LCD AC Timing Definitions
Table 23. LCD AC Timing Specifications
Symbol
Description
Min
Max
Units
Notes
Tpclkdv
Tpclkdv L_PCLK rise/fall to L_LDD<7:0>
driven valid
0
3.5
ns
1
Tpclklv
L_PCLK fall to L_LCLK driven valid
-0.5
2.0
ns
2
Tpclkfv
L_PCLK fall to L_FCLK driven valid
-0.5
2.0
ns
2
Tpclkbv
L_PCLK rise to L_BIAS driven valid
5.524
12
ns
2
NOTES:
1. Program the LCD data pins to be driven on either the rising or falling edge of the pixel clock (L_PCLK).
2. These LCD signals can, at times, transition when L_PCLK is not clocking (between frames). At this time,
they are clocked with the internal version of the pixel clock before it is driven out onto the L_PCLK pin.
A4775-01
L_LDD[7:0]
(rise)
L_LDD[7:0]
(fall)
L_PCLK
L_LCLK
L_BIAS
L_FCLK
Tpclkdv
Tpclklv
Tpclkfv
Tpclkbv
Tpclkdv
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