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參數(shù)資料
| 型號： | PW-82351-120 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 運動控制電子 |
| 英文描述： | BRUSHLESS DC MOTOR CONTROLLER, 150 A, XMA |
| 文件頁數(shù)： | 15/16頁 |
| 文件大小： | 273K |
| 代理商： | PW-82351-120 |
8
HALL SENSOR INPUTS (HA,HB,HC)
The HA, HB, HC inputs are connected to the Hall effect sensors
from the motor. A, B, C, correspond to the hall phasing. These
inputs are Schmitt triggered with hysteresis for noise immunity
as shown in FIGURE 4.
The hall sensors are used to translate the motor current sense
signals to the proper phase for the IA, IC, and ICOMP outputs,
see TABLE 7.
HALL FLAG
The Hall Flag in normal operation will drop low (logic 0). The Hall
Flag will set high (logic 1) when it detects the Hall sensor inputs,
HA, HB and HC to be either all highs or all lows.
VCC,RTN
The VCC and RTN (return) should be connected to the high cur-
rent system power supply. These pins are directly connected to
the output transistors and supply the power to the motor. A
capacitor should be placed between VCC and RTN as a reser-
voir for instantaneous high current switching (See DDC’s
Application Note AN/H-6,
PW-82351 Motor Drive Power
Supply). This capacitance should be located directly adjacent to
the motor drive to minimize the interconnect effects from line
inductance and resistance.
V
LPS
,V
PS+
,V
PS-
, DIG GND, ANA GND, POWER GND
The VLPS is the logic power supply input for the control section.
This point is connected to the +5 volt power supply. The VLPS
should have external decoupling.
The VPS+ and VPS- are the analog power supply inputs for the
control section. These inputs are connected to the ±15 volt
power supplies. Power for the internal DC-DC power supply is
also derived from the VPS+ input. The VPS+ and VPS- should
have external decoupling.
The ANA GND and DIG GND connection is a single point
power supply return for the VLPS, VPS+, and VPS-. POWER
GND is the return for internal DC-DC power supply. These
ground points must be tied together externally.
The PW-82351 will be fully functional within 1 ms after all
power supply voltages are applied.
VCC
Z
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
UA
UB
UC
LA
LB
LC
HA
HB
HC
INPUT SEL
DISABLE
/ENABLE
UMC
PHASE A OUT
PHASE B OUT
PHASE C OUT
12
3
4
5
6
VCC
RTN
FIGURE 5. PW-82351 INPUT TIMING DIAGRAM
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