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參數(shù)資料
| 型號： | PW-82351-120 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 運(yùn)動控制電子 |
| 英文描述： | BRUSHLESS DC MOTOR CONTROLLER, 150 A, XMA |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 273K |
| 代理商： | PW-82351-120 |
5
TABLE 3. DESCRIPTION OF DUAL FUNCTION PINS
MAIN
FUNCTION
ALTERNATE
FUNCTION
DESCRIPTION
UA
DIR
CONTROLS THE SWITCHING OF THE
PHASE A (UPPER) TRANSISTOR
CHANGES THE POLARITY OF THE
APPLIED VOLTAGE ACROSS THE MOTOR
LA
PWM
CONTROLS THE SWITCHING OF THE
PHASE A (LOWER) TRANSISTOR
DUTY CYCLE INPUT
UB
BRAKE
CONTROLS THE SWITCHING OF THE
PHASE B (UPPER) TRANSISTOR
SELECTS THE BRAKE MODE
LB
IDIR
CONTROLS THE SWITCHING OF THE
PHASE B (LOWER) TRANSISTOR
INVERTS THE POLARITY OF ICOMP
SIGNAL OUTPUT
UC
2Q-4Q
CONTROLS THE SWITCHING OF THE
PHASE C(UPPER) TRANSISTOR
2-QUADRANT AND 4-QUADRANT
MODULATION
LC
BRAKE
PWM
CONTROLS THE SWITCHING OF THE
PHASE C(LOWER) TRANSISTOR
BRAKE CURRENT CONTROL DUTY
CYCLE INPUT
DIR
A logic ‘0’ or ‘1’ at this input would establish the load voltage as
in TABLE 6.
IDIR
A logic ‘0’ at this input will generate an Icomp signal to match
TABLE 7 representative current, whereas a logic ‘1’ will gener-
ate ICOMP signal of opposite polarity.
PWM
An external fixed frequency square wave with varying duty
cycle is applied to this input. The signal can vary from 0% to
100% for similar voltage variation at the output.
BRAKE
The BRAKE input controls dynamic braking of the motor. A
logic ‘1’ at this pin will select the brake mode. In this mode, the
alternate inputs (DIR, IDIR, PWM, 2Q-4Q) will be ignored and
only the Brake PWM input will be used to PWM the lower
switches in the 3-phase bridge. The UMC input must be at a
logic low (0) when the brake mode is used.
BRAKE PWM
When operating in the brake mode, the BRAKE PWM input is
used to control the duty cycle of the lower switches in the 3-
phase bridge during braking. This input requires an external
fixed frequency square wave with varying duty cycle. It is
important to monitor the current returning from the load, and
provide an external current limit that sets the PWM BRAKE sig-
nal to a logic ‘0’ when currents higher than the PW-82351 rat-
ings are detected. A logic ‘0’ on this input will turn off all the
lower switches while a logic ‘1’ will turn on all the lower switch-
es simultaneously.
H = VCC, L = RETURN, X = IRRELEVANT, Z = HIGH IMPEDANCE (OFF)
LOGIC CONTROL INPUTS/COMMUTATION LOGIC
(UA / DIR, UB / BRAKE, UC / 2Q-4Q) (LA / PWM, LB /
IDIR, LC / BRAKE PWM)
The logic control inputs are dual function inputs that allow the
user to select external or internal control for the switching of
the output transistors. When INPUT SEL is a logic low (0), the
six logic inputs, (UA,UB, UC, LA, LB, LC) control the switching
of the output transistors. As shown in TABLE 4, a logic high
(1) turns on the output transistor, and a logic low (0) turns the
transistor off. The PW-82351 outputs PHASE AOUT, PHASE
BOUT and PHASE COUT are either a H (VCC), L (RTN), or Z
(OFF), depending on the logic input. However, when INPUT
SEL is a logic high (1), it enables the alternate input functions,
DIR, PWM, BRAKE, IDIR, 2Q-4Q, and BRAKE PWM as shown
in TABLE 3. All 6 logic control inputs have built-in noise filtering
as shown in FIGURE 2.
START UP LOGIC INITIALIZATION
When powering up the PW-82351, the DISABLE/ENABLE
input should be in the disable condition and the
Uncommanded Motion Control (UMC) input signal should be
delayed (see description on UMC operation). This will allow
time for the internal circuitry to reach operating voltage before
input signals are applied. During power up the internal under
voltage circuitry is activated until the +15 V power supplies
reaches +12 V. This feature is necessary to prevent damage
to the IGBT’s when the voltage powering the gate drivers
drops below a point that insures normal operation. Once nor-
mal operation is obtained (within 1 ms) the PW-82351 can be
enabled and all outputs will switch properly.
TABLE 4. PW-82351 INPUT-OUTPUT TRUTH TABLE
CONTROLS
INPUTS
OUTPUTS
UMC
INPUT
SEL
DIS/EN
UPPERS LOWERS PHASE
A OUT
PHASE
B OUT
PHASE
C OUT
UA UB UC LA LB LC
0
1
0
1
0
H
L
Z
0
1
0
1
H
Z
L
0
1
0
1
Z
H
L
0
1
0
1
0
L
H
Z
0
1
0
L
Z
H
0
1
0
1
0
Z
L
H
0
1
0
L
H
0
1
0
1
0
1
L
H
L
0
1
0
1
0
L
H
0
1
0
1
H
L
0
1
0
1
0
H
L
H
0
1
0
1
H
L
1
0
X
Z
1
0
1
X
Z
0
1
X
Z
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